JENN-GWO HWU2018-09-102018-09-102007https://www.scopus.com/inward/record.uri?eid=2-s2.0-33846300678&doi=10.1063%2f1.2404470&partnerID=40&md5=5d0c1c05d15a586273a7dc91ffcf92fdhttp://scholars.lib.ntu.edu.tw/handle/123456789/329946Stress testing is performed in two stages, a high-field prestress test followed by an electrostatic discharge (ESD) event, which induces high-field current impulse stress. dc and impulse high-field prestress sources are separately applied to generate different formations of bulk oxide traps, near-interface oxide traps (border traps), and interface traps. Experimental results indicate that the dc prestress testing induces many more interface traps and border traps in the metal-oxide-semiconductor capacitor structure than the impulse prestress testing. Additionally, an anomalous turnaround degradation of oxide breakdown subjected to the following ESD impulse stress is observed and attributed to the effect of border traps. Border traps cannot communicate with interface traps and silicon substrate during high-field current impulse stressing, and therefore cannot emit trapped charges instantaneously. Consequently, these trapped charges provide a negative electric field decreasing the Fowler-Nordheim stress current and therefore reducing the degradation of the oxide breakdown. © 2007 American Institute of Physics.Capacitors; Electric breakdown; Electrostatic devices; Interfaces (materials); MOS devices; Prestressing; Silicon compounds; Electrostatic discharge (ESD); High field current impulse stress; High field prestress tests; Stress testing; Electric dischargesjournal article10.1063/1.24044702-s2.0-33846300678