國立臺灣大學電機工程學系暨研究所汪重光2006-07-252018-07-062006-07-252018-07-062002-07-31http://ntur.lib.ntu.edu.tw//handle/246246/7894This project is for the 2nd of the three-year project that develops DMT-based xDSL transceiver architecture and explores analog front-end circuit design techniques including two key blocks in analog front-end, namely, tunable filter and magnitude control, will be designed. During the first period, the techniques of DSL transmission are studied. The architecture of the DMT-based xDSL transceiver is designed. The issues of VLSI circuit, namely, architecture and specifications, are investigated. Besides, practical circuit design considerations on low voltage and low power are taken into account. In the second period, the transceiver architecture is validated on a basis of computer simulation in conjunction with theoretical analysis. Moreover, analog front-end circuits are designed and simulated. The issues of bandwidth-tunable filtering and magnitude control are both investigated.application/pdf619357 bytesapplication/pdfzh-TW國立臺灣大學電機工程學系暨研究所Dual-loopAutomatic Gain Control (AGC)Programmable FilterVDSLDMTreporthttp://ntur.lib.ntu.edu.tw/bitstream/246246/7894/1/902218E002038.pdf