Dept. of Electr. Eng., National Taiwan Univ.Hsiao, M.-F.M.-F.HsiaoMarek-Sadowska, M.M.Marek-SadowskaSAO-JIE CHEN2018-09-102018-09-10200319483287http://www.scopus.com/inward/record.url?eid=2-s2.0-48349121765&partnerID=MN8TOARShttp://scholars.lib.ntu.edu.tw/handle/123456789/303244Crosstalk noise is a crucial factor affecting chip performance in deep submicron technologies. Among all possible crosstalk noise sources, clock is the most common aggressor as well as victim. Crosstalk on clock nets can increase clock jitter, which may degrade significantly the system performance. Besides, in modern chip designs, there is usually more than one clock net, and some-times even tens of them. It is therefore imperative to design clock topologies to prevent possible crosstalk among them. In this paper, we address the inter-clock crosstalk. We propose algorithms to design clock topology and to perform routing minimizing the effective crosstalk. Our experimental results show a significant reduction of clock jitter compared to the conventional clock tree synthesis which does not take into account the inter-clock crosstalk effects. © 2003 IEEE.application/pdf314018 bytesapplication/pdfCapacitance; Clocks; Coupling circuits; Crosstalk; Frequency; Jitter; Routing; Signal synthesis; Topology; WiresCapacitance; Coupled circuits; Crosstalk; Design; Jitter; Timing jitter; Topology; Wire; Chip performance; Clock tree synthesis; Crosstalk effect; Crosstalk noise; Deep sub-micron technology; Frequency; Routing; Signal synthesis; Clocksconference paper10.1109/ISQED.2003.11947542-s2.0-48349121765