電機資訊學院: 電子工程學研究所指導教授: 呂學士周承毅Jhou, Cheng-YiCheng-YiJhou2017-03-062018-07-102017-03-062018-07-102016http://ntur.lib.ntu.edu.tw//handle/246246/276287本篇論文提出兩個適用於逐漸趨近式類比至數位轉換器的類比及混合電路設計技術。根據實際的晶片量測結果，我們證實了這些技巧的應用性。 第一個技術是單位電容的布局方法。在不考慮製程變異的情況下，比照之前的設計，我們確保每個單位電容所處在的環境和其他的單位電容是相同的。採用此技術的類比至數位轉換器在1伏特的操作電壓下，其功率消耗為6.2μW，有效位元數為9.47 bits。其品質因數為43.7 fJ/conversion-step。 第二個技術是混合式電容切換程序。我們提出了一個電容切換程序可以減少因電容切換程序而造成在比較器上的動態偏差電壓。採用此技術的類比至數位轉換器在1伏特的操作電壓下，其功率消耗為6.0μW，有效位元數為9.51 bits。其品質因數為41.1 fJ/conversion-step。 這兩個設計都是在0.18μm 1P6M CMOS technology製作的。This thesis presents two analog and mixed-signal circuit design techniques for successive-approximation register (SAR) analog-to-digital converters (ADCs). According to the measurement results of the experimental prototypes, the presented techniques are verified. The first technique is the layout schemes of a unit capacitor. Compared to last work [1], the surroundings of a unit capacitor is identical to each unit capacitor, which does not take process variation into consideration. This relevant prototype SAR ADC consumes 6.2μW at 1-V supply, and the effective number of bit (ENOB) is 9.47 bits. The resultant figure of merit (FoM) is 43.7 fJ/conversion-step. The second technique is a hybrid capacitor switching procedure. In order to suppress the effect of dynamic offset in the comparator, a capacitor switching procedure is proposed. This relevant prototype SAR ADC consumes 6.0μW at 1-V supply, and the ENOB is 9.51 bits. The resultant FoM is 41.1 fJ/conversion-step. Both of the prototypes are implemented in a 0.18μm 1P6M CMOS technology.論文使用權限: 不同意授權逐漸趨近式類比至數位轉換器數位錯誤補償電容切換程序耦合寄生successive-approximation registeranalog-to-digital convertersdigital error correctioncapacitor switching procedurecouplingparasitic.thesis10.6342/NTU201602688