陳少傑臺灣大學：電子工程學研究所林呈光Lin, Cheng-KuangCheng-KuangLin2007-11-272018-07-102007-11-272018-07-102006http://ntur.lib.ntu.edu.tw//handle/246246/57479由於現今對於高傳輸頻寬及高速運作的需求，時間邊界（Timing Margin）亦相對受到了壓縮。不良的連線品質會影響到資料的傳輸速率，因此如何增進傳送與接收資料的品質成了一項重要的課題。延遲鎖定迴路可被用來校正時脈與資料間的相位誤差。 第一章為我的研究動機以及延遲鎖定迴路的應用。 在第二章中，會針對延遲鎖定迴路的基本原理做一介紹。藉由連續時域與離散時域模型的分析，可以了解其運作方式以及各參數對系統所造成的影響。 延遲鎖定迴路的各子方塊及其功用會在第三章中做介紹，電路設計的要點亦會予以討論。 第四章為延遲鎖定迴路整個系統的架構，各個子方塊電路的模擬結果會在此章呈現。 在第五章會介紹一個源同步點對點的平行傳輸介面，在第四章所設計的延遲鎖定迴路可被運用在此系統中以供連線相位誤差之補償。第六章為最後的結論。Nowadays, as the demand for high bandwidth links and high speed operation, the timing margin is shrinking. The poor performance of link will limit the data rate. How to improve the quality of transmitting and receiving data becomes an important issue. DLLs are one of the components that can be used to correct the timing skew of clock and data. In chapter 1, the motivation of why I choose this topic to research and the applications of DLLs are described. In chapter 2, the fundamental concepts of DLLs are introduced. The continuous-time and discrete-time models of a DLL are then presented to understand its behavior and research how its performance is affected by the system parameters. In chapter 3, each function block of a DLL and its functions are introduced. The design issues of each circuit are described. The entire system, each circuit block, and the simulation results are shown in chapter 4. In chapter 5, a source-synchronous point-to-point parallel link is introduced. The DLL designed in chapter 4 is utilized for skew-compensation. The algorithm for deskew is also introduced. Chapter 6 is my conclusion.ABSTRACT i LIST OF FIGURES v LIST OF TABLES viii CHAPTER 1 INTRODUCTION 1 1.1 Motivation 1 1.2 Comparison between PLLs and DLLs 3 1.3 Applications of DLLs 5 1.4 Thesis Organization 5 CHAPTER 2 BASICS OF DELAY-LOCKED LOOPS 7 2.1 Basic Principles of a DLL 7 2.2 S-domain Analysis of the DLL 7 2.3 Z-domain Analysis of the DLL 8 2.3.1 TypeⅠ DLL 9 2.3.2 TypeⅡ DLL 12 CHAPTER 3 DESIGN CONSIDERSATION 15 3.1 Startup Circuit 15 3.2 Phase Detector 17 3.2.1 Current Mode Logic 17 3.2.2 Phase Detector 20 3.2.3 Phase Offset of the PD 22 3.3 Delay Cell 22 3.3.1 Delay Cell with Symmetric Loads 24 3.3.2 Delay Cell with Negative-Resistance Load 26 3.4 Dummy Cell and Buffer 28 3.5 Level Shifter 30 CHAPTER 4 SIMULATION RESULTS 31 4.1 Startup Circuit 31 4.2 PD 32 4.3 CP and LF 34 4.4 VCDL 36 4.5 Close Loop Result 37 CHAPTER 5 DLL FOR INTERCONNECTION DESKEW 41 5.1 Source-Synchronous Point-to-Point Parallel Link 41 5.2 Skew Compensation 43 5.3 Phase Interpolation 44 5.3.1 Phase Averaging with Resistor String 47 5.3.2 Phase Interpolation with Resistor Ring 50 5.4 Coarse/Fine Phase Selection 54 CHAPTER 6 CONCLUSION 57 REFERENCE 594737266 bytesapplication/pdfen-US延遲鎖定迴路Delay-Locked Loopthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/57479/1/ntu-95-R93943090-1.pdf