陳少傑臺灣大學：電子工程學研究所楊雅嵐Yang, Ya-LanYa-LanYang2007-11-272018-07-102007-11-272018-07-102004http://ntur.lib.ntu.edu.tw//handle/246246/57639隨著科技的進步，數位無線區域網路通訊技術正在蓬勃地發展，為了因應系統單晶片時代的到來，近年來的設計傾向於把多個系統整合於單晶片的運用上，利用一些設計的技巧可以節省面積以及降低其操作所需的必v。 本論文主在描述一個可以整合IEEE 802.11b無線網路和Bluetooth短距離傳輸的多模組載波頻率回復電路。對二種規格中之數種調變，我們利用多模組的特殊設計及一些簡單的邏輯闡，使整塊迴路的操作頻率與輸入訊號的頻率相同，再利用輸入訊號形式的不同，選擇適當之相位偵測器來偵測出頻率的誤差。經迴路濾波器後，將訊號輸出到數值控制震盪器累加以查出所偏移的相位，最後由相位旋轉器調回原本所預期的載波頻率，達成回復的動作。本電路可用以抵抗數位無線通訊通道中的不理想因素，回復原本的頻率以便後端電路易於解調，同時能達到省電的效果。In this Thesis, we present a multimode carrier recovery circuit design with hardware implementation. We combine the two different Wireless LAN specifications: Bluetooth modulated in GFSK scheme and IEEE 802.11b modulated in several DPSK schemes. Using the input data mode to determine the suitable phase detector and loop filter bandwidth. We understand the bandwidth of loop filter plays an important role in this feedback loop. It dominates the loop stable time and helps the circuit to resist the channel noise. For low power consideration, gated clock is also used in this design, thus, the whole loop does not always operate on the highest frequency and the two-phase detector is not always on at the same time. The whole loop spends about 10~35 μs to reach the stable state and meet the specification, that requires 128μs for a long preamble in IEEE 802.11b and 64μs for Bluetooth.. The power required is 2.38mW when operating in 8MHz for Bluetooth, and 11.71mW for IEEE 802.11b. The total chip has an area of 0.48*0.48mm2 and contains 14175 gates.LIST OF CONTENTS ABSTRACT ……………………………………………………….……….....….. i LIST OF CONTENTS ………………….………………………………………… iii LIST OF FIGUIRES ………..…………………………………….……………. vi LIST OF TABLES ……………..…………………………………………….……. ix CHAPTER 1 INTRODUCTION ……………………………………….………. 1 1.1 Motivation ………………………………………………………………… 1 1.2 Thesis Organization ……………………………………………………..… 2 CHAPTER 2 WIRELESS LAN OVERVIEW ………………………………… 3 2.1 Introduction to Wireless Communication Systems ……………………… 3 2.2 The 802.11b WLAN ……………………………………………………… 7 2.2.1 Packet Format ……………………………………………………… 8 2.2.2 Direct Sequence Spread Spectrum Technology ……………………… 9 2.2.3 DPSK Modulation ……………………………………………….. 11 2.2.4 Backer Sequences ……………………………………………...... 15 2.2.5 CCK Modulation ……………………………………………….. 16 2.3 Bluetooth …………………………………………………………..…… 18 2.3.1 Packet Format …………………………………………………….. 18 2.3.2 Frequency Hopping Spread Spectrum Technology ……………….. 19 2.3.3 Gaussian Frequency Shift Keying Modulation ………………….…. 21 CHAPTER 3 CARRIER RECOVERY LOOP ……………………………….. 23 3.1 Channel Characteristics of WLAN ……………….……………………. 23 3.2 Carrier Recovery Loop …………………………………………………… 24 3.2.1 System Overview …………………………………………………… 25 3.2.2 System Analysis ……………………………………………………... 28 CHAPTER 4 MULTIMODE ARCHITECTURE …………………………..……. 33 4.1 Multimode Issue ………………………..…………….………………..…… 33 4.2 Multimode Carrier Recovery Structure ………………………………… 35 4.3 Gated Clock …………………………………………………………………. 36 4.4 De-Rotator ………………………………………………………………… 38 4.5 Phase Detector …………………………………………………………… 39 4.5.1 Modified Costas Detector …………………………………………… 40 4.5.2 Frequency Discriminator …………………………………………… 43 4.6 Loop Filter ………………………………………………………………… 45 4.7 NCO and Sine/Cosine Tables …………………………………………… 47 CHAPTER 5 HARDWARE IMPLEMENTATION …………………………… 51 5.1 Cell-Based Design Flow ………………………………………………… 51 5.2 Matlab Simulation Result ………………………………………………… 53 5.3 RTL Simulation Result ………………………………………………… 58 5.4 Physical Layout …………………………………………………………… 61 CHAPTER 6 CONCLUSION ………………………………………………… 63 REFERENCES ………………………………………………………………… 651500142 bytesapplication/pdfen-US頻率回復多模組無線區域網路MultimodeWireless LANCarrier Recovery Circuitthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/57639/1/ntu-93-R91943050-1.pdf