Teng N.-YWu Y.-TWang R.-XCHIH-TING LIN2021-09-022021-09-0220211530437Xhttps://www.scopus.com/inward/record.uri?eid=2-s2.0-85099727947&doi=10.1109%2fJSEN.2021.3052772&partnerID=40&md5=b11373b2139c71685b366f63103dea26https://scholars.lib.ntu.edu.tw/handle/123456789/580733As the CMOS-based ion-sensitive field-effect transistor (ISFET) is scaling down to achieve a compact sensing array with high spatial resolution, reduction of sensing layer capacitance attenuates capacitive coupling efficiency of environmental input signals and decreases sensitivity performance. To address this issue, a concept of three-dimensional (3D) sensing structure is proposed and examined in this study. This can increase the sensing layer capacitance for a given footprint area. Based on our designs, a series of 3D sensing structures can be implemented with a standard CMOS foundry service and CMOS-compatible post processes. Our experimental results show that an $8.5^{2}\mu \text{m}^{2}$ footprint design of the 3D sensing structure can obtain approximately 2-fold increase in transconductance compared with a traditional ISFET with the same footprint. This enables pH sensitivity to be improved 1.5-fold in current response and 1.15-fold in voltage response. Therefore, the proposed 3D-structure ISFET can pave the way toward an ISFET sensing array with high sensitivity and high spatial resolution. ? 2001-2012 IEEE.Capacitance; Image resolution; Ion sensitive field effect transistors; Capacitive couplings; Current response; High sensitivity; High spatial resolution; Sensing characteristics; Sensitivity performance; Threedimensional (3-d); Voltage response; CMOS integrated circuitsjournal article10.1109/JSEN.2021.30527722-s2.0-85099727947