國立臺灣大學電子工程學研究所張耀文2006-07-262018-07-102006-07-262018-07-102003-07-31http://ntur.lib.ntu.edu.tw//handle/246246/19984http://ntur.lib.ntu.edu.tw/bitstream/246246/19984/1/912215E002038.pdf可重組化系統（reconfigurable system）的架構可概分為可重組態的邏輯模組、一般的邏輯模組及各種 模組間資料傳輸的機制(如系統匯流排等)。其特點為整合多種功能（如微處理機、多媒體、通訊及記憶體 等），並利用可重組化模組time-sharing 的特性以增進可用邏輯的密度及彈性的大型電路設計。因此，此系 統的設計，須整合各種大型功能模組，並考慮可重組化模組執行時的各種時間先後順序限制 (temporal constraints) ，以達電路效能的最佳化。而如何有效地整合各類模組以節省晶粒的面積（die area），滿足系 統速度的要求，降低重組邏輯時的大量電力耗損，同時並防制各種電氣效應(如串音[crosstalk]，時脈不對稱 [clock skew],等)所造成的問題，為一重要待解的課題。本子計畫旨在探求可重組化系統於實體設計（physical design）層次所產生問題的解決方法，研究領域包含：（1）可重組化電路的實體設計，如考量時間先後順序 限制的佈局規劃及擺置等(temporal floorplanning/placement) ，（2）系統各模組的整合(含大型電路的佈局規 劃、擺置及繞線等)，及（3）系統及系統匯流排設計電氣效應的模擬。non-reconfigurable logic modules, and (reconfigurable) interconnections/system buses for connecting those modules. A reconfigurable system typically integrates modules of different functions (e.g., microprocessors, multimedia units, communication units, embedded memory, etc) and improve logic density and flexibility by time-sharing. For the design of such a system, we need to consider the integration of large-scale circuit modules and temporal constraints for circuit performance optimization. Therefore, it is desired to effectively integrate various functional modules to optimize silicon area, timing, power dissipation (especially the dissipation due to logic reconfiguration), and at the same time satisfy the design constraints induced from the electrical effects such as crosstalk, clock skew, etc. This subproject intends to study the issues in physical design for the reconfigurable system, including (1) physical design for reconfigurable circuits (temporal floorplanning and placement), (2) integration of logic modules (large-scale circuit floorplanning, placement, routing, etc., and (3) modeling of electrical effects for the reconfigurable system.application/pdf372260 bytesapplication/pdfzh-TW國立臺灣大學電子工程學研究所reconfigurable systemreconfigurable computingphysical designfloorplanningplacementroutingcrosstalkclock skew可重組化系統可重組化計算實體設計佈局規劃擺置繞線串音時脈不對稱reporthttp://ntur.lib.ntu.edu.tw/bitstream/246246/19984/1/912215E002038.pdf