C.-H. WengT.-A. WeiE. AlpmanC.-T. FuT.-H. LinTSUNG-HSIEN LIN林宗賢2019-10-242019-10-242016189200https://scholars.lib.ntu.edu.tw/handle/123456789/428185This paper presents an energy-efficient third-order 3 bit continuous-Time delta-sigma modulator (CTDSM). In this work, several architectural and circuit techniques are adopted to facilitate a low-power modulator. In the loop filter design, a single-Amplifier biquad (SAB) topology is incorporated to realize the desired transfer function. With the SAB architecture, only two amplifiers are needed for implementing a third-order CTDSM. Furthermore, in the proposed SAB, the excess-loop-delay (ELD) compensation is implemented without using an extra summing circuit. For the 3 bit quantizer, a time-domain quantizer is proposed, where the data-weighted-Averaging function is embedded in this quantizer to mitigate the nonlinearity issue due to the mismatch of digital-To-Analog converter (DAC) unit cells. Fabricated in a 90 nm CMOS technology and clocked at 300 MHz sampling frequency, the proposed SAB-based modulator achieves a 67.2 dB SNDR and a 69.3 dB SNR in an 8.5 MHz signal bandwidth. The overall CTDSM dissipates 4.3 mW and achieves a figure-of-merit of 135 fJ/conversion-step. © 1966-2012 IEEE.Delta-sigma modulation; excess loop delay; quantizer; single-Amplifier biquad[SDGs]SDG7Amplifiers (electronic); Continuous time systems; Delay circuits; Delta sigma modulation; Digital to analog conversion; Energy efficiency; Light amplifiers; Low power electronics; Summing circuits; Time domain analysis; Circuit techniques; Data weighted averaging; Delta sigma modulator; Excess loop delay; Excess loop delays (ELD); Quantizers; Sampling frequencies; Single amplifier biquad; Modulatorsjournal article10.1109/jssc.2016.25323452-s2.0-84977988609