Cruz, H.H.CruzYI-JAN EMERY CHEN2020-06-112020-06-112016https://scholars.lib.ntu.edu.tw/handle/123456789/501230This paper presents a 2.4 GHz receiver front-end fabricated in 0.13um CMOS process. The front-end incorporates a narrow-band LNA and a direct-conversion sub-harmonic passive mixer. The reduced number of devices of the mixer enhances the overall noise figure (NF) while low conversion loss is effectively achieved at the same time. Quadrature generation circuit blocks were included in the chip for testing purposes. The measured NF and input third-order intercept point (IIP3) of the CMOS receiver are 4.7 dB and -2.2 dBm, respectively. The power consumption of the front-end is 1mW under 1V supply voltage. The chip size is 0.91 mm × 0.61 mm.[SDGs]SDG7conference paper10.1109/RWS.2016.74443612-s2.0-84964583040https://www.scopus.com/inward/record.uri?eid=2-s2.0-84964583040&doi=10.1109%2fRWS.2016.7444361&partnerID=40&md5=ef59ad127208c925a08aa662d37a4882