李建模臺灣大學：電子工程學研究所邱銘豪Chiu, Min-HaoMin-HaoChiu2007-11-272018-07-102007-11-272018-07-102005http://ntur.lib.ntu.edu.tw//handle/246246/57571本論文提出跳躍式掃描(Jump-scan， 縮寫為J-scan)低功率可測試設計。 J-scan每時脈週期可傳送兩位元的掃描資料， 故可減半掃描之時脈頻率且不增加任何測試時間。 實驗數據顯示本設計相對於傳統之多工掃描(MUX-scan)可有效地降低67% 之測試功率， 並且只需要稍微修改MUX-scan之設計，不需要額外的計算即可達成； 伴隨J-scan而來的代價是面積的增加以及速度下降。This paper presents a Jump scan technique (or J-scan) for low power testing. The J-scan shifts two bits of scan data per clock cycle so the scan frequency is halved without increasing the test time. The experimental data show that the proposed technique effectively reduces the test power by 67% compared to the traditional MUX scan. The presented technique requires very few changes in the existing MUX-scan design for testability (DFT) methodology and needs no extra computation. The penalties are area overhead and speed degradation.摘要 II Jump Scan: A DFT Technique for Low Power Testing III Abstract III 1. Introduction 1 1.1 Motivation 1 1.2 J-scan 3 1.3 Contributions 4 1.4 Thesis Organization 5 2. Background 7 2.1 Power Dissipation 7 2.2 Past Research 9 2.2.1 Low power external testing techniques 9 2.2.2 Low power BIST techniques 13 2.3 MUX-scan DFF 15 3. J-scan technique 17 3.1 Jump-scan DFF and Jump-scan chain 17 3.2 JQN-scan DFF 22 4. Experimental results 25 4.1 Power Dissipation 25 4.2 Area overhead 29 4.3 Comparison against Other Techniques 30 4.4 Chip implementations 32 4.4.1 Low power transmitter design 32 4.4.2 Measurement result 37 5. Discussions and Future Work 42 5.1 Double Edge Trigger Scan FF 42 5.2 Double Data Rate Scan 43 5.3 Low Power BIST 44 6. Summary 54 Appendix I. Power Consumption Estimation Flow 56 Appendix II. Simulation Test Bench 57 References 58en-US低功率測試可測試設計自我測試Low Power TestingScanDFTDelay Fault TestingBISTthesis