電機資訊學院: 電機工程學研究所指導教授: 郭斯彥李彥融Lee, Yen-JungYen-JungLee2017-03-062018-07-062017-03-062018-07-062016http://ntur.lib.ntu.edu.tw//handle/246246/276546電路導線的可繞度是現今數位電路實體設計的重要課題。在擺置階段不考慮可繞度，可能會使得繞線階段導線密度過高壅塞而無法成功繞線，甚至導致重新擺置、不斷重複擺置與繞線。另一項重要課題是障礙物，包括已決定好位置的巨集電路。過往的巨集電路擺置演算法能有效處理放在晶片邊緣的障礙物，卻無法有效率的處理非晶片邊緣的障礙物。有些類比電路擺置演算法能有效處理非晶片邊緣的障礙物，然而這些演算法無法直接套用在巨集電路擺置。以手動擺置作為靈感、結合角落縫合、角落序列與四元樹演算法，我們提出能有效同時處理邊緣障礙物與非邊緣障礙物的近似線性時間複雜度巨集電路擺置演算法，並能針對可繞度來最佳化擺置結果。因為擺置演算法保證巨集電路之間不會重疊，模擬退火能專注於從沒有重疊的擺置結果中尋找最佳解、因而提昇演算法速度。雖然實驗沒有完成、無法與過往演算法完整比較，但是實驗仍證實了本演算法在平均情況下呈線性的時間複雜度。Routability of nets has become an important concern in modern digital circuit design. A placement solution with bad routability may cause congestion of nets and thus time is wasted in iterations between placement stage and routing stage. Another important concern in macro placement is blockage, or pre-placed macros. Previous works of macro placement handle boundary blockage well, but cannot cope with non-boundary blockage effectively. Though some works of analog placement are designed for non-boundary blockage, they cannot be applied to digital circuit design directly. By borrowing the concept of manual placement and integrating corner stitching, corner sequence and quadtrees together, the proposed method of this paper can deal with both boundary and non-boundary blockage effectively with average case linear time complexity, and at the same time keep good routability result for macro placement. Because the proposed method guarantees placing macros without overlap, simulated annealing can be sped up by focusing on finding the best result among valid solutions. However, experiments for comparing running time with previous works are not yet performed and thus the research of this paper is not complete.690548 bytesapplication/pdf論文公開時間: 2019/7/25論文使用權限: 同意有償授權(權利金給回饋學校)實體設計混合大小擺置巨集電路擺置可繞度障礙物模擬退火Physical DesignMixed-Size PlacementMacro PlacementRoutabilityBlockageObstacleSimulated Annealingthesis10.6342/NTU201600708http://ntur.lib.ntu.edu.tw/bitstream/246246/276546/1/ntu-105-R02921031-1.pdf