Lin, C.-Y.C.-Y.LinWang, T.-J.T.-J.WangHung, Y.-T.Y.-T.HungTSUNG-HSIEN LIN2021-05-052021-05-052020https://www.scopus.com/inward/record.url?eid=2-s2.0-85093694947&partnerID=40&md5=a07171ae858605ebfd5a05aed909570fhttps://scholars.lib.ntu.edu.tw/handle/123456789/559262An open-loop fractional output divider (FOD) using phase rotating technique is presented. A phase rotating technique is adopted to reduce the dynamic range of digitalto-Time converter (DTC) for output jitter improvement. This prototype is implemented in a 90-nm CMOS process. It can operate over a frequency range of 0.635 MHz to 162.5 MHz. At 160-MHz output frequency, it consumes 6.29 mW from 1-V supply. The measured phase noises at 1-MHz offset is 135.8 dBc/Hz and it achieves 1.19 psrms integrated jitter (10 kHz to 30 MHz). © 2020 IEEE.fractional output divider; phase rotating techniqueJitter; Phase noise; 90-nm cmos; Dynamic range; Fractional divider; Frequency ranges; Multiple outputs; Open-loop; Output frequency; Rotating technique; VLSI circuitsconference paper10.1109/VLSI-DAT49148.2020.91962132-s2.0-85093694947