汪重光Wang, Chorng-Kuang臺灣大學:電子工程學研究所袁芳立Yuan, Fang-LiFang-LiYuan2010-07-142018-07-102010-07-142018-07-102008U0001-2107200815164300http://ntur.lib.ntu.edu.tw//handle/246246/189030本篇論文將探討應用於IEEE 802.16-2004無線都會網路之多重輸入多重輸出（MIMO）正交分頻（OFDM）多工數位基頻接收機的實體層設計，以及其中256點2×2快速傅立葉轉換器（FFT）的硬體實做。先，內部接收機的設計包含了符元邊界偵測、循環字首模式偵測、載波頻率漂移/取樣頻率漂移之估計與補償、相位補償、多重輸入多重輸出通道估計、Alamouti時空區塊編碼（STBC）信號解碼以及區塊最小均方差（BLMS）適應性等化器。利用時空前置碼（STC preamble）的特性，一個2×2多重輸入多重輸出通道的頻率響應可以透過最小平方法（LS）以及數值内插技術很輕易地被估計出來。其次，區塊最小均方差演算法被利用來幫助Alamouti時空區塊編碼頻域等化器（FEQ）執行適應性通道追蹤。根據系統模擬結果，使用適應性等化技術在符元錯誤率（SER）的表現上明顯優於沒有使用適應性等化技術的作法。著，本篇論文提出一個低複雜度的2×2 MIMO FFT/IFFT處理器。由於傳統radix-2管線架構（pipeline architecture）的硬體使用率僅有50%，為了處理兩條資料路徑的傅立葉轉換將會需要兩套硬體同時運算，或是一套硬體但提高其內部工作頻率（意即折疊運算技術：folding processing），因此複雜度往往較高。然而，本篇論文所提出的資料路徑排程技術（dataflow scheduling, DS）可以有效地使得硬體利用率由50%提升到100%，因此僅需要一套硬體即可完成兩條資料路徑的運算，而降低硬體複雜度。之外，在實際的硬體架構設計中，大容量的延遲緩衝器（delay buffer）將會使用單埠暫存器檔案（single-port register file）來實做，並且透過硬體分享的技巧將所需要的複數乘法器個數減少。篇論文亦展示了在FFT/IFFT處理器中的改良複數乘法器的設計。此設計使用了一些硬體技巧，包含了資料對應（data mapping），signed-digit表示法以及實虛部共同項分享（common-term sharing）。與傳統乘法器相比，此改良乘法器在晶片面積上僅剩65%。後，此提出之FFT/IFFT處理器已在FPGA板上驗證無誤，並且達到預計的44dB SQNR要求。後端晶片設計部分則使用標準0.18微米CMOS製程技術，其中核心面積為887×842微米平方。根據佈局後模擬結果，本設計在64 MHz工作頻率以及1.8 V供應電壓的情況下，共計消耗46 mW。In the thesis, a 2x2 MIMO OFDM digital baseband receiver for IEEE 802.16-2004 WMAN-OFDM PHY applications is designed. The hardware implementation of a 256-point 2x2 MIMO FFT/IFFT processor is also presented. he inner receiver design includes the symbol boundary detection, CP mode detection, CFO/SFO estimation/compensation, phase compensation, MIMO channel estimation, Alamouti-scheme STBC detector and BLMS adaptive equalization. Based on the format of space-time coding (STC) preamble, the frequency response of the 2x2 MIMO channel can be easily estimated by performing least-square (LS) estimation and piecewise-parabolic interpolation. On the other hand, the BLMS algorithm is derived to adaptively track the estimated channel coefficients for the Alamouti-scheme STBC frequency-domain equalizer (FEQ). According to the simulation results, the 2x2 STBC-based BLMS adaptive FEQ can achieve superior improvement of the SER performance over non-adaptive ones. Subsequently, a cost efficient MIMO FFT/IFFT processor for IEEE 802.16 WMAN is presented. Considering the conventional radix-2 pipeline architectures, the hardware utilization is only 50%. However, by applying the proposed dataflow scheduling (DS) technique, the effective hardware utilization can be raised to 100%. Therefore, a single butterfly unit within each pipeline stage is sufficient to deal with the two data sequences, and the hardware complexity is significantly reduced. Besides, the single-port register files are employed for the large-size delay buffers in order to lower the area cost and power consumption. The hardware-sharing technique is also applied to reduce the required complex multipliers. n addition, the design of a modified complex multiplier is presented. Some hardware design techniques are applied, including the data mapping scheme, signed-digit representation and common-term sharing between the real and the imaginary parts of the twiddle factor. The modified complex multiplier requires only 65% of the cell area compared with the conventional one. he proposed FFT/IFFT processor has been emulated on the FPGA board. The SQNR performance is over 44 dB for QPSK and 16/64-QAM signals, which can achieve 0.1 dB of implementation loss. Furthermore, a test chip has been designed using standard 0.18-um CMOS technology with a core area of 887x842 um^2. According to the post-layout simulation results, the design consumes 46 mW under 1.8 V supply voltage at 64 MHz operating frequency.1 Introduction 1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Thesis Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 MIMO OFDM Technology 9.1 MIMO Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.1 Channel Capacity . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.2 Space Diversity . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.3 Spatial Multiplexing and Space-Time Coding . . . . . . . . . . . . 13.2 OFDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.1 OFDM Signal Modeling . . . . . . . . . . . . . . . . . . . . . . . 16.2.2 Guard Interval and Cyclic Prefix . . . . . . . . . . . . . . . . . . 18.3 MIMO OFDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Physical Layer Speci cations of IEEE 802.16-2004 WMAN-OFDM 21.1 OFDM Symbol Description . . . . . . . . . . . . . . . . . . . . . . . . . 21.1.1 Time domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.1.2 Frequency domain . . . . . . . . . . . . . . . . . . . . . . . . . . 22.2 System Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.2.1 Frame Structure (Down-Link) . . . . . . . . . . . . . . . . . . . . 23.2.2 Preamble Format . . . . . . . . . . . . . . . . . . . . . . . . . . . 25.3 Architecture of the Inner Transmitter . . . . . . . . . . . . . . . . . . . . 26.3.1 Pilot Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 27.3.2 Constellation Mapper . . . . . . . . . . . . . . . . . . . . . . . . . 28.3.3 Alamouti-Scheme Space-Time Coding . . . . . . . . . . . . . . . . 28.3.4 Inverse Discrete Fourier Transform . . . . . . . . . . . . . . . . . 31.3.5 Interpolation Filter . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Wireless Channel Model 33.1 SISO Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34.1.1 Large-Scale Fading: Path Loss and Shadowing . . . . . . . . . . . 34.1.2 Small-Scale Fading: Multipath Fading . . . . . . . . . . . . . . . 35.1.3 Power Delay Pro le (PDP) . . . . . . . . . . . . . . . . . . . . . . 37.1.4 Rayleigh Fading and Ricean Fading . . . . . . . . . . . . . . . . . 40.1.5 Additive White Gaussian Noise . . . . . . . . . . . . . . . . . . . 44.2 Transmitter/Receiver Non-ideal E ects . . . . . . . . . . . . . . . . . . . 45.2.1 Carrier Frequency O set . . . . . . . . . . . . . . . . . . . . . . . 45.3 Sampling Frequency O set . . . . . . . . . . . . . . . . . . . . . . . . . . 47.4 MIMO Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48.5 Digital Baseband Channel Modeling . . . . . . . . . . . . . . . . . . . . . 49 MIMO OFDM Digital Baseband Inner Receiver Design 53.1 Receiver Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53.2 Synchronization for Acquistion . . . . . . . . . . . . . . . . . . . . . . . . 56.2.1 Symbol Boundary O set . . . . . . . . . . . . . . . . . . . . . . . 56.2.2 Carrier Frequency O set . . . . . . . . . . . . . . . . . . . . . . . 60.3 Discrete Fourier Transform . . . . . . . . . . . . . . . . . . . . . . . . . . 65.4 Synchronization for Residual Error Tracking . . . . . . . . . . . . . . . . 67.4.1 Residual CFO and SFO Estimation . . . . . . . . . . . . . . . . . 67.4.2 Carrier Recovery Loop for Residual CFO Compensation . . . . . 69.4.3 Phase Compensation and Timing Regulation . . . . . . . . . . . . 71.5 Channel Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73.5.1 Interpolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74.6 Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77.6.1 STBC Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77.6.2 Block Least-Mean-Square Adaptive Equalization . . . . . . . . . . 79 Hardware Implementation of FFT/IFFT Processoror MIMO OFDM Systems 85.1 Functional Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . 86.2 Fast Fourier Transform Algorithm . . . . . . . . . . . . . . . . . . . . . . 87.3 Review of Prior Arts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91.3.1 Architecture for Implementation . . . . . . . . . . . . . . . . . . . 91.3.2 Previous Design of MIMO FFT Processor . . . . . . . . . . . . . 98.4 Proposed Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103.4.1 Concept of Dataw Scheduling . . . . . . . . . . . . . . . . . . . 103.4.2 Design Example:-Point Dataw Scheduling FFT Processor . . . . . . . . . . . . 107.4.3 Proposed Architecture:56-Point MRDS FFT/IFFT Processor . . . . . . . . . . . . . . . 108.4.4 Summary and Comparison . . . . . . . . . . . . . . . . . . . . . . 108.5 Fixed Point Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111.5.1 SQNR Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . 111.5.2 Dynamic Range in IFFT Operation . . . . . . . . . . . . . . . . . 112.5.3 Dynamic Range in FFT Operation . . . . . . . . . . . . . . . . . 115.5.4 Simulation Result . . . . . . . . . . . . . . . . . . . . . . . . . . . 115.6 RTL Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118.6.1 Selection of Storage Element . . . . . . . . . . . . . . . . . . . . . 119.6.2 Control Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . 120.6.3 Processing Element . . . . . . . . . . . . . . . . . . . . . . . . . . 122.6.4 Complex Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . 124.6.5 Low Power/Area Considerations . . . . . . . . . . . . . . . . . . . 128.6.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134.7 FPGA Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135.8 Chip Design and Performance Comparison . . . . . . . . . . . . . . . . . 137 Conclusion 1415741285 bytesapplication/pdfen-US多重輸入多重輸出正交分頻多工時空區塊編碼區塊最小均方差快速傅立葉轉換MIMOOFDMSTBCBLMSFFTthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/189030/1/ntu-97-R95943003-1.pdf