Low-Latency Voltage-Racing Winner-Take-All (VR-WTA) Circuit for Acceleration of Learning Engine

Chia-Heng WuTing-Sheng ChenDing-Yuan LeeAn-Yeu (Andy) WuAN-YEU(ANDY) WU吳安宇2019-10-242019-10-242017https://scholars.lib.ntu.edu.tw/handle/123456789/427747Low-Latency Voltage-Racing Winner-Take-All (VR-WTA) Circuit for Acceleration of Learning Engineconference paper10.1109/vlsi-dat.2017.79396412-s2.0-85021411330