A 0.13μm hardware-efficient probabilistic-based noise-tolerant circuit design and implementation with 24.5dB noise-immunity improvement

AN-YEU(ANDY) WUWey, I.-C.I.-C.WeyChen, Y.-G.Y.-G.ChenYu, C.C.YuChen, J.J.ChenWu, A.-Y.A.-Y.WuAN-YEU(ANDY) WU2018-09-102018-09-102007http://www.scopus.com/inward/record.url?eid=2-s2.0-51349132683&partnerID=MN8TOARShttp://scholars.lib.ntu.edu.tw/handle/123456789/332570[SDGs]SDG7A 0.13μm hardware-efficient probabilistic-based noise-tolerant circuit design and implementation with 24.5dB noise-immunity improvementconference paper10.1109/ASSCC.2007.4425694