Dept. of Electr. Eng., National Taiwan Univ.Chen, Shuenn-ShiShuenn-ShiChenChen, Jong-JangJong-JangChenChen, Sao-JieSao-JieChenTsai, Chia-ChunChia-ChunTsai2007-04-192018-07-062007-04-192018-07-061999-01http://ntur.lib.ntu.edu.tw//handle/246246/2007041910021556A Pin-Grid-Array (PGA) package router is presented in this paper. Given a chip cavity with a number of I/O pads around its boundary and an equivalent number of pins distributed on the substrate, the objective of the router is to complete the planar interconnection of pad-to-pin nets on one or more layers. This router consists of three phases: layer assignment topological routing, and geometrical routing. Examples tested on a windows-based environment show that our router is efficient and can complete the routing task with less substrate layers. Compared to manual routing, this router features a friendly graphic user interface and can be practically applied to VLSI packaging.application/pdf400710 bytesapplication/pdfen-USjournal article10.1109/ASPDAC.1999.759783