MTCMOS low-power optimization technique (LPOT) for 1V pipelined RISC CPU circuit

C. B. HsuY. S. HongJ. B. KuoJAMES-B KUO2018-09-102018-09-102014-12http://scholars.lib.ntu.edu.tw/handle/123456789/388606MTCMOS low-power optimization technique (LPOT) for 1V pipelined RISC CPU circuitconference paper10.1109/icecs.2014.70499212-s2.0-84925438872