Chang S.-WLu T.-HYang C.-YYeh C.-JHuang M.-KMeng C.-FChen P.-JChang T.-HChang Y.-SJhu J.-WHong T.-ZKe C.-CYu X.-RLu W.-HBaig M.ACho T.-CSung P.-JSu C.-JHsueh F.-KChen B.-YHu H.-HWu C.-TLin K.-LMa W.C.-YLu D.-DKao K.-HLee Y.-JLin C.-LHuang K.-PChen K.-MLi YSamukawa SChao T.-SHuang G.-WWu W.-FLee W.-HJIUN-YUN LIShieh J.-MTarng J.-HWang Y.-HYeh W.-K.2023-06-092023-06-0920211631918https://www.scopus.com/inward/record.uri?eid=2-s2.0-85127000636&doi=10.1109%2fIEDM19574.2021.9720675&partnerID=40&md5=d1ccb0e69f564821f184478c3d328754https://scholars.lib.ntu.edu.tw/handle/123456789/632441In this work, we demonstrate vertically stacked heterogeneous dual-workfunction gate complementary FET (CFET) inverters and 6T-SRAM with n-Type IGZO and p-Type polysilicon channels for the first time. The dual-workfunction gate structure with adjusted gate biasing allows the adjustment of channel potential to match the threshold voltage of transistors for CMOS and SRAM operation. High-frequency IGZO RF devices with p-Type silicon isolation are fabricated simultaneously with the same process. Novel etching process based on fluorine-based gas with an extremely high-etching selectivity between the source/drain metal and the IGZO facilitates the definition of the source/drain region. IGZO surface treated with fluorine-based gas during over-etching step allows a low leakage current shallow passivation layer to optimize direct current characteristics. © 2021 IEEE.Etching; Fluorine; Leakage currents; Passivation; Semiconducting indium compounds; Thin film transistors; Three dimensional integrated circuits; 3-D integration; 6T-SRAM; 6T-SRAMs; Fluorine-based gas; Low power RF; Low-power SRAM; Monolithics; RF applications; SRAM applications; Ultra-low power; Threshold voltageFirst Demonstration of Heterogeneous IGZO/Si CFET Monolithic 3D Integration with Dual Workfunction Gate for Ultra Low-power SRAM and RF Applicationsconference paper10.1109/IEDM19574.2021.97206752-s2.0-85127000636