Zero-Aware Asymmetric SRAM Cell for Reducing Cache Power in Writing Zero

Chang, Yen-JenYen-JenChangLai, FeipeiFeipeiLaiFEI-PEI LAI2009-02-272018-07-062009-02-272018-07-062004http://ntur.lib.ntu.edu.tw//handle/246246/142053http://ntur.lib.ntu.edu.tw/bitstream/246246/142053/1/17.pdfapplication/pdf958729 bytesapplication/pdfen-USZero-Aware Asymmetric SRAM Cell for Reducing Cache Power in Writing Zerojournal article10.1109/TVLSI.2004.831471http://ntur.lib.ntu.edu.tw/bitstream/246246/142053/1/17.pdf