陳少傑臺灣大學：電子工程學研究所謝宜政Hsieh, Yi-ChengYi-ChengHsieh2007-11-272018-07-102007-11-272018-07-102005http://ntur.lib.ntu.edu.tw//handle/246246/57349光通訊收發機系統中，時脈與資料回復電路的設計是最錯綜複雜的零件。未來10GBASE-LX4乙太網路在數千兆位元的區域網路光通訊系統中扮演相當重要的角色。由於低成本、低功率、及高度整合的優勢，我們使用TSMC 0.18μm 1P6M CMOS製程來實現此高速的電路。 　　因為系統要求位元錯誤率要小於十的負十二次方，這將使的時脈與資料回復電路設計上更加困難。而此篇論文使用了雙迴路追溯路徑來達到更好的抖動效能。而新設計的相位偵測器可降低控制線上的漣波使得電壓控制振盪器穩定震盪。我們同時也設計一個雙端控制的兩級延遲單元環形電壓控制振盪器，此震盪器具備低功率消耗、大的調變區域、以及更好的相位雜訊效能。 　　使用長度為二的七次方減一的PRBS資料輸入，在鎖定後的回復輸出時脈具有峰對峰值為2.2ps的抖動。使用1.8伏的電源，整個時脈與資料回復電路有75mW功率消耗。同時晶片的使用面積為0.75mm x 0.75mm。The design of Clock and Data Recovery (CDR) circuits is the most complicated part of an optical transceiver. In the near future, 10GBASE-LX4 Ethernet will play an important role in the multi-gigabit optical communication system of Local Area networks (LANs). We use TSMC 0.18μm 1P6M CMOS technology to implement this high speed circuit to achieve low cost, low power consumption, and highly integrated capability. Since the required Bit Error Ratio (BER) must be less than 10-12, there will be a serious design challenge for the CDR. This Thesis presents a CDR architecture which has dual loop tracking path to achieve better jitter performance. The new phase detector (PD) which reduces the control line ripples makes the VCO oscillating steadily. We also design a two-stage ring VCO with a dual-control node to have low power dissipation, wide tuning range, and better phase noise performance. The recovery clock exhibits a peak to peak jitter of 2.2ps for a PRBS sequence of length 27-1. The CDR circuit dissipates a total power of 75mW with a 1.8V supply and occupies a die area of 0.75 mm x 0.75 mm.TABLE OF CONTENTS ABSTRACT ..…………………………………………………………………… i LIST OF FIGURES ..…………….………………………...………………... v LIST OF TABLES ..…………………………………………………….……. ix 1. INTRODUCTION …..……………………………………………..……... 1 1.1 Motivation ..……..…………………………………………..……… 1 1.2 Generic Optical System ……………………………………………. 2 1.3 Overview of Thesis …..…...…………...…………………………..... 3 2. CDR IN 10GBASE-LX4 ARCHITECTURE ….…………………………. 5 2.1 10GBASE-LX4 Architecture ……..…………………………………. 5 2.1.1 Overview …………...…..……………………………………. 5 2.1.2 PMD and MDI ……..……..…………………………………. 7 2.1.3 10GBASE-LX4 Architecture …..……………….…………….. 10 2.1.4 Jitter Specification ..………….……………………………….. 12 2.2 Generic CDR Architecture ....….…………………………….……… 14 2.2.1 CDR Architecture ..….……………………………….………... 15 2.2.2 Full-Rate and Half-Rate CDR Architectures ……....….……… 16 2.2.3 Referencedless and Referenced CDR Architectures ………….. 17 2.3 Clock and Data Recovery Building Blocks …………….…..…….. 20 2.3.1 Phase Detectors ..……………………………………..……….. 20 2.3.2 Frequency Detectors ..……….…………………….….….…… 23 2.3.3 Voltage Controlled Oscillator ...….…..….….….....…............... 25 2.3.4 Proposed CDR Architecture ..…………………………..……. 26 3. CDR CIRCUIT DESIGN .……………………………………..………… 27 3.1 Behavior Model of CDR Blocks …………....…..…………………… 27 3.2 Jitter Generation ..……………………………………………..…..... 31 3.3 Jitter Transfer ..…………….………………..……………………… 32 3.4 Jitter Tolerance …...………..……………..………………………… 33 4. BLOCKS OF DUAL-TRACKING PATH CDR CIRCUIT DESIGN .….. 35 4.1 Phase Detector and Voltage to Current Converter .........…………… 35 4.1.1 General Consideration ...…...………………….……………… 35 4.1.2 PD Circuit Design ..………………………..………………..… 35 4.1.3 Phase Error in the Voltage to Current Converter Circuit …..…. 38 4.2 Voltage Controlled Oscillator ...………………………….…....…… 41 4.3 Loop Filter and Jitter Performance Simulation ..…..…….….……… 46 4.4 Frequency Divider Circuit Design ………...……………..………… 49 4.5 Frequency Detector Circuit Design …..……………………….…… 51 4.6 Lock Detector …..………….………………………………..……… 53 5. IMPLEMENTATION OF THE CDR CIRCUIT ………………..………… 57 5.1 CDR Closed Loop Behavior Simulation Results ....….…..………… 57 5.2 CDR Closed Loop Transistor Level Simulation Results ……….….. 60 5.3 Chip Layout of the Proposed CDR ……….….………….………… 62 5.4 Performance Summary ……………………………….……………. 63 6. CONCLUSION ………………………………………….………………… 65 REFERENCE ………………………………………………….……………….. 67en-US時脈與資料回復電路CDRthesis