Shao-Ku KaoBo-Jiun ChenSHEN-IUAN LIU2018-09-102018-09-102007-0715497747http://scholars.lib.ntu.edu.tw/handle/123456789/333719https://www.scopus.com/inward/record.uri?eid=2-s2.0-34547583530&doi=10.1109%2fTCSII.2007.895326&partnerID=40&md5=6b3bc6e1524e4298e1b7d5365caa1081An anti-reset all-digital delay-locked loop (DLL) is presented. When the input clock frequency changes significantly, the dynamic frequency detector re-locks the DLL without any external reset signal. The proposed binary time-to-digital converter (BTDC) reduces effectively the hardware, compared with a conventional TDC. Unlike many previous all-digital DLLs, this one is a closed feedback loop that can track environmental variations. The input frequency range can be operated from 62.5-625 MHz. It spends at most six cycles to synchronize the input and output clocks. © 2007, IEEE. All Rights Reserved.[SDGs]SDG15Closed loop control systems; Detector circuits; Feedback control; Synchronization; Delay-locked loop; Dynamic frequency detector; Frequency range; Time-to-digital converter; Delay circuitsjournal article10.1109/tcsii.2007.8953262-s2.0-34547583530WOS:000248235500002