臺灣大學: 電子工程學研究所林宗賢林振堅Lin, Chen-ChienChen-ChienLin2013-04-102018-07-102013-04-102018-07-102012http://ntur.lib.ntu.edu.tw//handle/246246/256669在本論文中提出了一個符合藍牙應用的三階多位元的連續時間三角積分調變器，對於傳統多位元連續時間三角積分調變器中數位類比轉換器部分，因為其電路本身非線性會使整體的調變器產生不必要的雜訊，導致電路訊號雜訊比會大大的降低，所以傳統電路會加入動態元件匹配電路，確保此電路的線性度。但是加入元件匹配電路，會影響到量化器的比較的時間。而在先進製程中，數位量化器 (時間數位轉化器) 相較於傳統的類比量化器有其優勢。因此本論文將時間數位轉化器和動態元件匹配電路做結合，形成一個天生具有動態元件匹配的時間數位轉化器。除此之外，使用數位量化器去輔助傳統量化器，可以減少量化器數目，進而使得功率消耗降低。 此三角積分調變器使用台積電90 nm互補式金氧半製程所實現，其使用64 MHz的取樣頻率在1 MHz的頻寬下可以得到69.6 dB的訊號雜訊比和72 dB的動態範圍，在類比1.2伏特和數位1伏特的供應電源時，只需要消耗1.8毫瓦的功率，且FoM為361 fJ/conv。A third-order multi-bit continuous-time delta-sigma modulator is presented in this thesis. Because the non-linearity of digital-to-analog circuit (DAC) degrades the performance of the signal to noise distortion ratio, conventional modulators adopt dynamic element matching technique to alleviate the problem. However, it consumes extra loop delay for dynamic element matching circuit, so the conversion time of the quantizer is squeezed. On the other hand, digital converters (time-to-digital converter) outperform analog converters in advanced processes. Therefore, in this thesis, inherently dynamic element matching time-to-digital converter-based quantizer is proposed. In addition, this work proposes a new technique to reduce the quantizer level by two-step quantizer, leading to area and power reduction. This continuous-time delta-sigma modulator is implemented in a TSMC 90-nm CMOS process. The proposed modulator achieves a 69.6-dB peak SNDR with a 1-MHz bandwidth at a 64-MHz sampling rate and has an 72-dB dynamic range. The implemented modulator dissipates only 1.8 mW from a analog 1.2-V and digital 1-V supply. FoM is 360 fJ/conv.3829832 bytesapplication/pdfen-US三角積分調變器時間數位轉換器Delta-sigma modulatorTime-to-digital converterthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/256669/1/ntu-101-R98943029-1.pdf