Gupta MVITA PI-HO HU2021-09-022021-09-022019https://www.scopus.com/inward/record.uri?eid=2-s2.0-85100862695&doi=10.1109%2fS3S46989.2019.9320675&partnerID=40&md5=a37ccebfbd604da90510c14b815a8995https://scholars.lib.ntu.edu.tw/handle/123456789/581199In this work, through calibrated simulations, comparative analysis of n-type Negative Capacitance (NC) Junctionless (JL) and Inversion Mode (IM) transistor is performed for Low Power (LP) applications. Through systematic metholdology and physical insights, it is highlighted that NC JL device exhbits negative internal gate voltage (Vint) at zero applied external gate bias (Vgs), which is benefical to achieve significantly lower value of off-current (Ioff) than NC IM device for LP applications. It is demonstrated that negative Vint in NC JL device can further be utilized to lower the gate workfunction to mid-gap level while achieving the and Ion ? 1.3 mA/μm at lower Ioff ? 10 pA/μm. The work showcases the opportunites to achieve the International Roadmap for Devices and Systems (IRDS) traget at gate length (Lg) of 20 nm and drain bias (Vds) of 0.1 V for designing LP systems and circuits using NC JL transistor. ? 2019 IEEE.Microelectronics; Comparative analysis; Devices and systems; Gate length; Gate voltages; Gate workfunction; Inversion modes; Low power application; Negative capacitance; Capacitanceconference paper10.1109/S3S46989.2019.93206752-s2.0-85100862695