Chen, Tung-ChienTung-ChienChenChen, Yu-HanYu-HanChenTsai, Sung-FangSung-FangTsaiSHAO-YI CHIENLIANG-GEE CHEN2009-02-252018-07-062009-02-252018-07-06200710518215https://www.scopus.com/inward/record.uri?eid=2-s2.0-34247556136&doi=10.1109%2fTCSVT.2007.894044&partnerID=40&md5=9ed6fb4505abc4c69fc1b55eb2aa0c0bhttp://scholars.lib.ntu.edu.tw/handle/123456789/329277http://ntur.lib.ntu.edu.tw/bitstream/246246/141473/1/61.pdfIn an H.264/AVC video encoder, integer motion estimation (IME) requires 74.29% computational complexity and 77.49% memory access and becomes the most critical component for low-power applications. According to our analysis, an optimal low-power IME engine should be a parallel hardware architecture supporting fast algorithms and efficient data reuse (DR). In this paper, a hardware-oriented fast algorithm is proposed with the intra-/inter-candidate DR considerations. In addition, based on the systolic array and 2-D adder tree architecture, a ladder-shaped search window data arrangement and an advanced searching flow are proposed to efficiently support inter-candidate DR and reduce latency cycles. According to the implementation results, 97% computational complexity is saved by the proposed fast algorithm. In addition, 77.6% memory bandwidth is further saved with the proposed DR techniques at architecture level. In the ultra-low-power mode, the power consumption is 2.13 mW for real-time encoding CIF 30-fps videos at 13.5-MHz operating frequency. © 2007 IEEE.application/pdf1264707 bytesapplication/pdfISO/IEC 14496-10 AVC; ITU-T Rec. H.264; Motion estimation (ME); VLSI architectureInteger motion estimation (IME); ISO/IEC 14496-10 AVC; ITU-T Rec. H.264; Video encoder; Algorithms; Bandwidth; Computational complexity; Computer hardware; Image coding; Trees (mathematics); VLSI circuits; Motion estimationjournal article10.1109/TCSVT.2007.8940442-s2.0-34247556136http://ntur.lib.ntu.edu.tw/bitstream/246246/141473/1/61.pdf