Chien, Ruei TingRuei TingChienLin, Mao JanMao JanLinYeh, Yang MingYang MingYehYI-CHANG LU2023-07-182023-07-182022-01-019786165904773https://scholars.lib.ntu.edu.tw/handle/123456789/633898In many hardware aligners, on-chip traceback is not supported because it requires large memory usage. The issue becomes even worse for three-sequence alignment, which is an algorithm to improve the accuracy of multiple sequence alignment. In this paper, we propose a design to reduce the usage of traceback memory for three-sequence alignment with affine gap penalty models. Using the pre-computed results from the forward dynamic programming stage, we are able to encode traceback directions with fewer bits. Our algorithm could save 37.5% memory usage when compared to direct implementations. The proposed bit-reduction method can be further combined with existing region-reduction traceback methods to lower required memory sizes.conference paper10.23919/APSIPAASC55919.2022.99801132-s2.0-85146280162https://api.elsevier.com/content/abstract/scopus_id/85146280162