國立臺灣大學應用力學研究所楊照彥2006-07-262018-06-292006-07-262018-06-292005-07-31http://ntur.lib.ntu.edu.tw//handle/246246/21732本文利用三維分子動力法,採用多體勢能;原子嵌 入法,來模擬物理氣相層積中賤鍍的過程,主要探討 在不同的阻絕層下,銅金屬原子於金屬連結中通道上 之薄膜成長研究,而其中影響金屬薄膜的形貌之相關 物理參數,如基板溫度、入射動能。由於原子嵌入法 所須的計算量非常龐大,本文亦利用不同分子動力模 擬平行計算方式,來加速計算效能,比較其計算之加 速性。由結果可知;所發展的計算程式碼及計算環境, 已可為下一階段利用量子模擬建立基礎。本計劃成果 已發表兩篇論文在”Materials Science in Semiconductor Processing”(SCI)。The rapid scaling of Si-based CMOS devices has led to silicon dioxide gate insulating film less than 2.0-nm thick. By year 2008, the 70-nm generation needs alternative gate dielectric material with higher K value than that of silicon dioxide. Traditional TCAD tool is not sufficient and atomic scale modeling and simulation is needed for the IC design and analysis. In first year (I), we have carried out the molecular dynamics simulation using empirical interatomic potential and tight binding theory to study the thin-film deposition. PC cluster tool is established for parallel implementation. The results indicate that the computational environment and simulation model and code have been completed and provide the basis for next stage quantum modeling/DFT simulation.application/pdf757230 bytesapplication/pdfzh-TW國立臺灣大學應用力學研究所閘極介電層之原子尺度模式與模擬(3/3)Atomic Scale Modeling and Simulation of the Gate Dielectrics (3/3)reporthttp://ntur.lib.ntu.edu.tw/bitstream/246246/21732/1/932212E002006.pdf