CSIE Dept., National Taiwan Univ.Chang, Yen-JenYen-JenChangYang, Chia-LinChia-LinYangLai, FeipeiFeipeiLai2007-04-192018-07-052007-04-192018-07-052003http://ntur.lib.ntu.edu.tw//handle/246246/200704191002950http://ntur.lib.ntu.edu.tw/bitstream/246246/200704191002950/1/01231826.pdfLow power caches have become a critical component of both hand-held devices and high-performance processors. Based on the observation that an overwhelming majority of the data written to the cache are '0', in this paper we propose a power-aware SRAM cell with one single-bitline write port and one differential-bitlines read port, called SWDR cell, to minimize the cache power consumption in writing '0'. The SWDR cell uses a circuit-level technique, which is software independent and orthogonal to other low power techniques at architecture-level. Compared to the conventional SRAM cell, the experimental results show that without compromise of both performance and stability, the SWDR cell can result in 73%-92% reduction in average cache write power dissipated in bitlines. © 2003 ACM.application/pdf437624 bytesapplication/pdfen-USBridge circuits; Circuit stability; Data mining; Energy consumption; Microprocessors; Permission; Random access memory; Tail; Voltage; Writing[SDGs]SDG7Bridge circuits; Cells; Cytology; Data mining; Electric potential; Energy utilization; Hand held computers; Microprocessor chips; Power electronics; Power management; Random access storage; Static random access storage; Technical writing; Cache power consumption; Circuit stability; Critical component; High performance processors; Low power techniques; Permission; Random access memory; Tail; Low power electronicsjournal article10.1109/LPE.2003.1231826http://ntur.lib.ntu.edu.tw/bitstream/246246/200704191002950/1/01231826.pdf