李建模臺灣大學：電子工程學研究所林柏州Lin, Po-ChouPo-ChouLin2007-11-272018-07-102007-11-272018-07-102005http://ntur.lib.ntu.edu.tw//handle/246246/57404由於電視調諧器須要處理大量的電視頻道，故其相位雜訊之測試十分的耗時且昂貴。本論文針對複雜的單晶片電視調諧器之相位雜訊提出一階層式的模擬方法。根據此模擬方式所得到的結果，進而提出一經濟有效的相位雜訊測試方法以節省量產測試的時間。此測試方法能決定出最有效的頻道及頻率進行測試，以減少相位雜訊的測試次數。對部分商用電視調諧器的電路樣本進行實驗，其結果顯示本論文所提出的方法能使測試時間降為約原來的十分之一，並且不會發生測試逃脫。Phase noise testing for TV tuners is time consuming and expensive because of the great number of TV channels. This thesis presents a hierarchical simulation method for a complicated single chip TV tuner. Based on the simulation results, an effective and economic test method is proposed to save the test application time. This method determines the most effective channels and frequencies to test so the number of phase noise measurements is reduced. Experimental results on commercial chips show that our proposed method reduces the test time by ten times without test escapes.誌謝 I 摘要 III Abstract IV Table of Contents V List of Figures VII List of Tables VIII Chapter 1 Introduction 1 1.1 TV Tuner 1 1.2 Motivation 3 1.3 Contributions 3 1.4 Organization 4 Chapter 2 Background 5 2.1 Circuit Structure 5 2.2 Phase Noise Concepts 8 2.2.1 Open Loop VCO 9 2.2.2 Phase Locked Loop 10 2.3 Past Research 14 Chapter 3 Proposed Methodology 18 3.1 Hierarchical Simulation Methods 18 3.1.1 VCO Simulation 19 3.1.2 PLL Simulation 21 3.1.3 Tuner Chip Phase Noise Calculation 23 3.2 Determine TV Channels to Test 25 3.3 Determine Offset Frequencies 27 Chapter 4 Experimental Results 29 4.1 Confirmation of Simulation Results 29 4.2 Test Results 34 Chapter 5 Discussions and Future Work 37 5.1 Discussion 37 5.1.1 Pass Ratio and Test Time 37 5.1.2 Generalization of Proposed Methodology 38 5.1.3 Volume Production Test 38 5.2 Future Work 39 Chapter 6 Summary 40 Appendix Measurement Results From Other Tuner Chip 41 References 55713943 bytesapplication/pdfen-US相位雜訊測試方法測試電視調諧器phase noisetesting methodologytestingtv tunerthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/57404/1/ntu-94-R92943079-1.pdf