An upper-bound algorithm for gate-level delay analysis

Dept. of Comput. Sci., National Taiwan Univ.Lu, SunshinSunshinLuLai, FeipeiFeipeiLai2007-04-192018-07-052007-04-192018-07-051989-05http://ntur.lib.ntu.edu.tw//handle/246246/2007041910032152application/pdf296900 bytesapplication/pdfen-USAn upper-bound algorithm for gate-level delay analysisjournal article10.1109/VTSA.1989.68620http://ntur.lib.ntu.edu.tw/bitstream/246246/2007041910032152/1/00068620.pdf