Dept. of Electr. Eng., National Taiwan Univ.Fang, H.-C.H.-C.FangChang, Y.-W.Y.-W.ChangCheng, C.-C.C.-C.ChengChen, C.-C.C.-C.ChenLIANG-GEE CHEN2018-09-102018-09-10200515206149http://www.scopus.com/inward/record.url?eid=2-s2.0-33646755881&partnerID=MN8TOARShttp://scholars.lib.ntu.edu.tw/handle/123456789/313904Memory issue is the most critical problem for a high performance JPEG 2000 architecture. The tile memory occupies more than 50% of area in conventional JPEG 2000 architectures. To solve this problem, we propose a stripe pipeline scheme. For this scheme, a Level Switch Discrete Wavelet Transform (LS-DWT) and a Code-block Switch Embedded Block Coding (CS-EBC) are proposed. With small additional memory, the LS-DWT and the CS-EBC can process multiple levels and code-blocks in parallel by an inter-leaved scheme. As a result of above techniques, the overall memory requirements of the proposed architecture can be reduced to only 8.5% comparing with conventional architectures. © 2005 IEEE.application/pdf607001 bytesapplication/pdf[SDGs]SDG7Data storage equipment; Embedded systems; Pipeline processing systems; Problem solving; Signal encoding; Wavelet transforms; Embedded Block Coding; Level Switch Discrete Wavelet Transform (LS-DWT); Memory efficient JPEG 2000 architecture; Stripe pipeline scheme; Computer architectureconference paper10.1109/ICASSP.2005.14162252-s2.0-33646755881