顧孟愷臺灣大學：資訊網路與多媒體研究所阮國興Juan, Kuo-HsingKuo-HsingJuan2007-11-272018-07-052007-11-272018-07-052007http://ntur.lib.ntu.edu.tw//handle/246246/58412The decoding algorithm of Low-Density Parity-Check (LDPC) codes is an iterative procedure. Therefore if the number of iterations can be reduced, the decoding throughput can be increased proportionally. The layered decoding algorithm is a fast converging decoding schedule which can reduce the number of iterations in half and has better coding gain performance than the conventional decoding schedule, two phase schedule. In this thesis, a LDPC decoder architecture using a fast converging layered decoding algorithm is presented. This hierarchical architecture is highly scalable and configurable. Two-level hierarchical quasi-cyclic LDPC codes are used to provide good coding gain and low error floor at long codeword length. We also develop a novel compensation method, mixedmode min sum algorithm, which can provide better BER performance and need less iterations than the scaling min sum. Several designs are implemented on Altera Stratix II EP2S130 FPGA. The LDPC decoder implementation with 2 first level decoding blocks and 32 second level decoding units can achieve close to 1 Gbps information throughput.Abstract i Contents ii List of Figures v List of Tables ix 1 Introduction 1 1.1 Overview of Channel Coding 2 1.2 Overview of LDPC Codes 3 1.2.1 Low-Density Parity-Check Matrix 3 1.2.2 Structured LDPC Codes 4 1.3 Overview of LDPC Decoding Algorithm 7 1.3.1 Hard Decision Decoding 7 1.3.2 Soft Decision Decoding 8 1.4 Motivation 11 1.5 Organization of Thesis 13 2 LDPC Soft Decision Decoding Algorithm 14 2.1 Sum Product Algorithm 14 2.1.1 Two Phase Schedule 15 2.1.2 Horizontal Layered Schedule 17 2.1.3 Vertical Layered Schedule 20 2.1.4 Simulation results 24 2.2 Min Sum Algorithm 24 2.3 Decoder Design Issue 28 2.3.1 Decoding Unit implementation 28 2.3.2 Architecture Design 30 3 Hierarchical Decoder Architecture Design 31 3.1 Code Matrix and Decoder Architecture 32 3.1.1 Hardware-friendly H-QC LDPC Codes 32 3.1.2 Semi-parallel Architecture for QC LDPC Codes 37 3.1.3 Semi-parallel Architecture for H-QC LDPC Codes 40 3.2 Hierarchical Decoder Architecture 42 3.2.1 First Level Processing 42 3.2.2 Second Level Processing 44 3.3 Second Level Decoding Units 44 3.3.1 Check Functional Unit 47 3.4 Early Termination Unit 50 3.4.1 Iteration-based Syndrome Test 50 3.4.2 Layer Distributed Syndrome Test (LDST) 50 3.4.3 Hard Decision Aided LDST 51 3.4.4 Simulation results 51 3.4.5 Throughput and Early Termination 52 3.5 Memory Structure 54 3.5.1 Layer Memory 55 3.5.2 Check Memory 55 3.5.3 Rotation ROM 56 3.6 Scheduling 56 4 FPGA Implementation Results 58 4.1 FPGA Design Flow 59 4.1.1 Algorithm Level Simulation 59 4.1.2 Architecture Design 60 4.1.3 Hardware C model Simulation 62 4.1.4 RTL model simulation 63 4.1.5 FPGA verification 65 4.2 FPGA Verification 66 4.2.1 Development Environment 66 4.2.2 Verification Scheme 67 4.3 Implementation Results and Analysis 68 4.3.1 Min Sum Compensation Algorithms 68 4.3.2 Early Termination Schemes 69 4.3.3 Minimum Search Units 70 4.3.4 Two-phase and layered schedules 71 5 Conclusion and Future Work 73 5.1 Conclusion 73 5.2 Future Work 751746001 bytesapplication/pdfen-US低密度奇偶校驗碼解碼器架構分層解碼LDPCLayered DecodingDecoder ArchitectureQC LDPCSemi-Parallelthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/58412/1/ntu-96-R94944007-1.pdf