黃俊郎臺灣大學：電子工程學研究所游源祺Yu, Yuan-ChiYuan-ChiYu2007-11-272018-07-102007-11-272018-07-102007http://ntur.lib.ntu.edu.tw//handle/246246/57581在本論文中，我們提出了一個針對1-bit/stage的管線式類比數位轉換器的全數位校正技術，它是從一個既有的數位校正演算法所延伸而來的。原本的方法在校正完後仍會留有些許輸出字碼遭受到異常大的非線性錯誤，而所提出的方法依據輸出字碼的統計直方圖將這些有瑕疵的輸出字碼取出，並根據瑕疵的程度做出不同處理以增加線性度。除了輸入信號以外，其他所有的校正運作都是在數位的範圍裡，並且整體的運作速度與類比數位轉換器本身的轉換速度相同。這個方法不需要對類比數位轉換器本身的類比部份做出任何修改，並且十分容易延伸至其他不同架構的管線式類比數位轉換器。分析的結果顯示出最大的微分非線性誤差將小於最小字碼單位長度的三分之一，而軟體模擬的結果也顯示積分非線性誤差至少會有一個位元精準度的改善。在最後一個可行的硬體實現架構也被提出。In this thesis, a fully digital calibration scheme for the 1-bit/stage pipelined ADC is presented. It is extended from the existing digital calibration algorithm that still suffers arbitrary large DNL in some output codes. The proposed technique extracts these codes from the histogram data and then applies proper modification to them to enhance the linearity. Except for the input ramp signal, the whole calibration is performed in the digital domain and is done at the nominal ADC speed. The approach does not require any modification to the original analog section of the ADC and is convenient to be extended to the different structures of the pipeline stage. The analysis exhibits a bound of 1/3 LSB in the DNL. Simulation result also shows at least 1-bit improvement in the INL. The digital hardware implementation scheme is presented as well.誌謝 I 中文摘要 II ABSTRACT III TABLE OF CONTENTS IV LIST OF FIGURES VI LIST OF TABLES VII CHAPTER 1 INTRODUCTION 1 1-1 MOTIVATION 1 1-2 SHORT SUMMARY OF THE PROPOSED METHOD 2 CHAPTER 2 PRELIMINARIES 3 2-1 STATIC TESTING OF ADC 3 2-2 FUNDAMENTALS OF PIPELINED ADC 5 2-2.1 Ideal Pipelined ADC 5 2-2.2 A Simplified Model for Each Sage 6 2-2.3 Error Sources of the Pipelined ADC 8 2-2.4 Conventional Calibration Technique 10 2-2.4.1 Coefficient Extraction 14 2-2.5 Problem of Conventional Technique 14 CHAPTER 3 PROPOSED EXTERNAL CALIBRATION TECHNIQUE 16 3-1 DEFINITION OF JUNCTION CODES 16 3-2 THE PROPOSED JUNCTION CODES FIX TECHNIQUE 16 3-2.1 Determine the Junction Codes 17 3-2.2 Further Processing of the Junction Codes 19 3-2.3 Performance Analysis 21 3-2.3.1 DNL Analysis 21 3-2.3.2 INL Analysis 22 3-2.3.3 Extra Memory Usage for Type 1 Codes 24 3-2.4 Overlap Cancellation 24 3-2.5 Generating the Error Coefficients 27 3-2.6 Calibration Coefficients Extraction Algorithm 27 3-2.7 Limited Hardware Resources 28 3-3 DETERMINE NUMBER OF STAGES TO CALIBRATE 30 CHAPTER 4 SIMULATION RESULTS 33 4-1 SIMULATION RESULTS OF JUNCTION CODES PROCESSING 33 4-2 SIMULATION RESULTS OF LIMITED HARDWARE RESOURCE 36 CHAPTER 5 DIGITAL CALIBRATION CIRCUIT IMPLEMENTATION SCHEME 39 5-1 THE CONVENTIONAL DIGITAL CALIBRATION SCHEME 39 5-2 THE PROPOSED DIGITAL CALIBRATION SCHEME 41 5-3 SYNTHESIS RESULT 42 CHAPTER 6 CONCLUSION AND FUTURE WORK 44 REFERENCES 45657486 bytesapplication/pdfen-US管線式 類比數位轉換器 校正pipeline ADC Calibrationthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/57581/1/ntu-96-R94943156-1.pdf