A 2 V clock synchronizer using digital delay-locked loop

Dept. of Electr. Eng., National Taiwan Univ.Hwang, Chorng-SiiChorng-SiiHwangChung, Wang-ChihWang-ChihChungWang, Chih-YongChih-YongWangTsao, Hen-WaiHen-WaiTsaoLiu, Shen-IuanShen-IuanLiu2007-04-192018-07-062007-04-192018-07-062000-08http://ntur.lib.ntu.edu.tw//handle/246246/2007041910021483application/pdf355071 bytesapplication/pdfen-USA 2 V clock synchronizer using digital delay-locked loopjournal article10.1109/APASIC.2000.896916http://ntur.lib.ntu.edu.tw/bitstream/246246/2007041910021483/1/00896916.pdf