國立臺灣大學電機工程學系暨研究所陳少傑2006-07-252018-07-062006-07-252018-07-061999-07-31http://ntur.lib.ntu.edu.tw//handle/246246/7711幾年來，由於積體電路製程技術以 及VLSI 設計技術之進步，使得電子零 組件之功能愈形豐富，性能也不斷提 升，複雜度也愈來愈高。一個系統晶片 可包括處理器或ASIP、ASIC、記憶體、 介面及聯結系統等。一個最佳化的應用 系統必須把運算工作適當地分配到處 理器或ASIP上的軟體及ASIC內的硬體 去執行。 目前的設計環境缺少專為硬體－ 軟體同步設計的需要而發展之輔助工 具，因此設計生產力與效率偏低。所以 硬體－軟體同步設計的主要研究就是 如何定義出描述系統規格 (System specification）之工具及如何完成硬體－ 軟體間的分工合作（Hardware-Software partitioning）。這通常需要一個能夠處 理硬體－軟體同步模擬（Co-simulation） 的環境來支援硬體－軟體分工合作的 驗證及分析其成效。Recently, due to the progress of VLSI design and fabrication technologies, the functions of electronic components become more and more complicated. Thus, the complexity of design increases much rapidly. A system-onchip usually comprises of a processor core, application-specific instruction set processor (ASIP), some ASICs, memory, interface, and their interconnections. A system designer is required to optimally divide the application tasks into software (S/W) and hardware (H/W) components and to distribute them to the processor core (or ASIP) and ASIC, respectively. Nowadays, little CAD tools are designed for the H/W-S/W co-design, leading to low productivity and long development time. The main research objectives of H/W-S/W co-design are as follows: (1) define a language suitable for H/W-S/W specifications, (2) accomplish the H/W-S/W partitioning, and (3) need a H/W-S/W co-simulation environment to evaluate the correctness and efficiency of the H/W-S/W partitioning and synthesis results.application/pdf34466 bytesapplication/pdfzh-TW國立臺灣大學電機工程學系暨研究所reporthttp://ntur.lib.ntu.edu.tw/bitstream/246246/7711/1/882215E002037.pdf