臺灣大學: 電子工程學研究所李建模劉威孝Liu, Wei-HsiaoWei-HsiaoLiu2013-04-102018-07-102013-04-102018-07-102010http://ntur.lib.ntu.edu.tw//handle/246246/257085軟性薄膜電晶體技術相較於傳統的矽技術有許多的優點，例如較低的成本以及較短的製作時間。隨著技術的發展，現今的軟性薄膜電晶體技術已經可以實做出相當複雜的數位電路。目前軟性薄膜電晶體技術最大的問題在於當薄膜電晶體受到彎曲時會造成漂移率的改變，所以當晶片受到彎曲時就會改變電路的時序。要避免出現設置時序錯誤就必須降低操作頻率，這篇論文提出一個軟性薄膜電晶體數位電路的擺位最佳化軟體來減少操作頻率必須降低的百分比。提出的技術支援三種最佳化模式，使用者可以根據不同的晶片封裝以及當晶片在運作時對彎曲的假定來選擇最佳化模式。在這篇論文中使用工研院提供的有機薄膜電晶體建立一個標準元件函式庫。實驗的結果顯示，當整張晶片都必須是軟性的時候，操作頻率需要降低的百分比可以降到原本的一半，而當一部份的晶片可以被固定在硬性的封裝時，操作頻率需要降低的百分比可以降到低於4%。就我們目前所知，這是第一個用於軟性薄膜電晶體數位電路的擺位最佳化的軟體。Flexible TFT technology has many advantages over conventional silicon technology such as low cost and short manufacturing time. As the technology advances, flexible TFT technology now has the ability to implement large-scale digital circuits. Currently the most important problem of flexible TFT technology is the change in mobility when the TFT is bent, and thus the circuit timing is changed when the chip is bent. A placement optimization of flexible TFT digital circuits is proposed to reduce the percentage of clock frequency that has to be slowed down in order to avoid setup time violations. Three optimization modes are supported by the proposed technique for the designer to choose based on different package and bending assumption. A standard cell library is characterized using an OTFT model provided by industrial technology research institute in this thesis. Our experimental results show that the percentage of clock frequency that has to be slowed down is reduced by half when the whole chip is flexible and below 4% when part of the chip is fixed to a rigid package. To the author’s knowledge, this is the first placement optimization tool for flexible TFT digital circuits.1761329 bytesapplication/pdfen-US擺位最佳化軟性薄膜電晶體技術數位電路Placement OptimizationFlexible TFT TechnologyDigital Circuitshttp://ntur.lib.ntu.edu.tw/bitstream/246246/257085/1/ntu-99-R97943075-1.pdf