顧孟愷臺灣大學：電機工程學研究所吳坤霖Wu, Kun-LinKun-LinWu2007-11-262018-07-062007-11-262018-07-062007http://ntur.lib.ntu.edu.tw//handle/246246/53420In SoC design, HW/SW interface design is error-prone. Different OS and bus system provide different HW/SW interface. Different IPs have different speed, data rate, throughput. Integrating them into a SoC system by hands is time-consuming and error-prone. We propose our HW/SW interface synthesis methodology for SoC design to solve this problem. Our methodology focuses on reusability, portability, and automation. We provide automation tools for bus interface synthesis and device driver synthesis. Bus interface synthesis tool improve IP integration flow, and improve IP reusability via the IP library. The data direct-connection and bottleneck detection technology are also provided to improve the system performance. The device driver synthesis tool, Expert template, can efficiently generates device driver for each IP via XML tags. The driver synthesis tool is OS independent. That means designer only need to implement one version device driver for different OS. We design some experiments to prove our methodology. The result shows our tools surely improve the SoC design.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 SoC design methodology . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3 Thesis organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Related work. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 Embedded OS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.1 uClinux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1.2 MicroC/OS-II . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1.3 eCos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 Bus system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.1 AMBA bus system . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2.2 Avalon bus system . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2.3 CoreConnect bus system . . . . . . . . . . . . . . . . . . . . . 14 2.2.4 Wishbone bus system . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.5 VCI interface protocol . . . . . . . . . . . . . . . . . . . . . . 15 2.3 Latest status of HW/SW interface synthesis . . . . . . . . . . . . . . 16 2.3.1 Communication Interface Generation For HW/SW Architec- ture In The STARSoC Environment . . . . . . . . . . . . . . . 16 2.3.2 Automation of IP Core Interface Generation for Reconfig urable Computing . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.3 Code generation for Linux device driver . . . . . . . . . . . . . 17 2.3.4 HW/SW interface synthesis based on avalon bus speci‾cation for Nios-oriented SoC design . . . . . . . . . . . . . . . . . . . 18 3 HW/SW interface synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1 Hardware IP interface synthesis . . . . . . . . . . . . . . . . . . . . . 19 3.1.1 Bus component logic design . . . . . . . . . . . . . . . . . . . 20 3.1.2 Bus connection . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.1.3 Data buffering FIFO . . . . . . . . . . . . . . . . . . . . . . . 22 3.1.4 IP classification . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.1.5 Data buffering FIFO content design . . . . . . . . . . . . . . . 26 3.1.6 Data path direct-connection . . . . . . . . . . . . . . . . . . . 30 3.1.7 Automatic hardware interface synthesis tool design . . . . . . 33 3.2 Expert template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.2.1 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.2.2 XML parser . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.2.3 XML tags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.2.4 Device driver template . . . . . . . . . . . . . . . . . . . . . . 40 4 Experimental result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.1 Development environment . . . . . . . . . . . . . . . . . . . . . . . . 42 4.1.1 Development FPGA board . . . . . . . . . . . . . . . . . . . . 42 4.1.2 Third party tools . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.2 IP resource . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.2.1 RS codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.2.2 AES codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.3 Case study and experimental result . . . . . . . . . . . . . . . . . . . 45 4.3.1 Hardware interface synthesis architecture . . . . . . . . . . . . 45 4.3.2 Data path direct-connection . . . . . . . . . . . . . . . . . . . 48 4.3.3 Buffered and unbuffered driver . . . . . . . . . . . . . . . . . . 51 4.3.4 Bus master and bus slave . . . . . . . . . . . . . . . . . . . . 52 4.3.5 OS portability . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5 Conclusion and Future work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.2 Future work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56950491 bytesapplication/pdfen-US系統晶片設計介面合成驅動程式合成匯排流介面合成作業系統獨立匯排流獨立SoC Designinterface synthesisdevice driver synthesisbus interface synthesisOS independentbus independentthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/53420/1/ntu-96-R94922150-1.pdf