呂學士Lu, Shey-Shi臺灣大學:電子工程學研究所王裕翔Wang, Yu-HsiangYu-HsiangWang2010-07-142018-07-102010-07-142018-07-102009U0001-2008200911554800http://ntur.lib.ntu.edu.tw//handle/246246/189219在台積電0.18微米互補式金氧半製程下，我們實現了一個具有電流泵自動校正電路之分數型頻率合成器。基於在校正時我們使用同一個電流泵，通道長度調變效應造成的電流泵不匹配將被消除。實驗結果顯示，經過校正後的參考突波為-82dBc，即下降了26dB。此頻率合成器可以產生2.125到2.575GHz的四相位輸出，利用24位元的三角積分調變器，其最小頻道距離可小於1Hz。而在1MHz頻率偏移處量測到的相位雜訊為-114dBc/Hz。最後，本頻率合成器達到所有藍牙應用相關的規範。 此外，我們提出兩個可重組的多頻帶低雜訊放大器，來克服傳統上應用於多規格的射頻前端電路所遭遇的大功率干擾訊號帶來的問題。方法是利用可調式主動核心電路把一個「寬頻」接收機分成幾個「窄頻」接收機。其中第一個低雜訊放大器可以接收所有軟體定義無線電使用的頻率，而第二個低雜訊放大器包含了所有於1.9到5.8GHz的應用。兩個低雜訊放大器都是在聯電90奈米互補式金氧半的製程下實現。實驗結果顯示，在我們使用的頻段下，雜訊指數為2.0到3.6dB，而輸入三階內插點為-0.5到-4.8dBm。A fractional-N frequency synthesizer with charge pump calibration technique is implemented in TSMC 0.18um CMOS technology. The CP mismatch due to channel-length modulation is eliminated because we use the same CP during calibration process. The measured output reference spur is -82dBc and improved by 26 dB after the calibration is done. Quadrature outputs can be generated from 2.125 to 2.575GHz. The minimum frequency step is less than 1Hz due to a 24-bit ΔΣ modulator. The measured phase noise is -114 dBc/Hz at an offset frequency of 1 MHz. All the related specifications are met in the application for Bluetooth. In addition, two reconfigurable multiband LNAs are proposed to conquer the AM blocker problem suffered in the conventional multi-standard RF front-end designs. The concept is dividing a “wideband” into several “narrowbands” by applying tunable active core. The first LNA is for all SDR band and the second LNA covers applications in 1.9 to 5.8GHz. Both of two LNAs are implemented in UMC 90nm process. The measured noise figure is from 2.0 to 3.6 dB and the measured IIP3 is from -0.5 to -4.8 dBm throughout the whole band of interest.誌謝 v要 viiBSTRACT ixONTENTS xiIST OF FIGURES xvIST OF TABLES xixhapter 1 Introduction 1.1 Motivation 1.2 Thesis Organization 2hapter 2 Phase-Locked Loop Fundamentals 5.1 Operating Principles of the PLL 6.2 General Considerations 8.2.1 Phase Noise 8.2.2 Spurs 10.2.3 Lock Time 12.3 Building Blocks of Charge Pump PLL 14.3.1 Phase/Frequency Detector (PFD) 14.3.2 Charge Pump (CP) 17.3.3 Loop Filter 21.3.4 Frequency Divider 22.3.5 Voltage-Controlled Oscillator (VCO) 28hapter 3 A Fractional-N Frequency Synthesizer for Bluetooth Receiver with Charge Pump Calibration 37.1 Introduction 37.2 Charge Pump Calibration Technique 38.3 Circuit Implementation 41.3.1 Architecture 41.3.2 Switched-delay PFD 42.3.3 Programmable Charge Pump 43.3.4 Bang-bang Phase Detector 44.3.5 SAR Controller for CP Calibration 45.3.6 VCO with Switched-capacitor Array 46.3.7 Auto Frequency Calibration (AFC) 50.3.8 Multi-Modulus Frequency Divider 52.3.9 Delta-Sigma Modulator (DSM) 54.3.10 Quadrature Generation 56.3.11 Loop Filter 58.4 Experimental Results 59.5 Summary 69hapter 4 A Reconfigurable Multiband Low-noise Amplifier with Tunable Active Core 71.1 Introduction 71.2 Basics of Narrow-Band LNA 72.2.1 Input Matching 72.2.2 Gain 75.2.3 Noise 77.2.4 Linearity 79.3 Circuit Implementation 84.3.1 Reconfigurable LNA I 84.3.2 Reconfigurable LNA II 86.4 Simulation & Experimental Results 87.4.1 Reconfigurable LNA I 88.4.2 Reconfigurable LNA II 90.5 Summary 95hapter 5 Conclusion 97EFERENCES 992878116 bytesapplication/pdfen-US分數型頻率合成器電流泵校正多頻帶低雜訊放大器fractional-Nfrequency synthesizercharge pump calibrationmultibandlow-noise amplifierthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/189219/1/ntu-98-R96943057-1.pdf