陳少傑臺灣大學：電子工程學研究所楊子震Yang, Tzu-ChenTzu-ChenYang2007-11-272018-07-102007-11-272018-07-102006http://ntur.lib.ntu.edu.tw//handle/246246/57452在現今的積體電路設計中，系統單晶片(SoC)是一個主流方向。鎖相迴路及相關的電路更是必須朝向SoC方面發展。隨著製程進步，電晶體的尺寸越來越小但對於被動元件的尺寸來說沒有變小。低通濾波器是鎖相迴路其中的一個區塊，是由電容以及電阻所組成。在過去的幾年中，為了降低晶片面積跟成本通常將低通濾波器設計在晶片外部。為了達到SoC的目的，希望將迴路濾波器整合進入晶片當中。然而，這些迴路濾波器在晶片當中佔了相當大的面積。由於在展頻時脈產生器中，通常會有一個較小的頻寬。所以在較小的頻寬下會造成較大的低通濾波器。如果我們欲降低此迴路濾波器的面積，可以利用一個除二電路來達到此目的。Today System-on-Chip (SoC) is a mainstream for integrated-circuit design. PLLs are essential for SoC. The transistor size becomes much smaller when the CMOS process is improved, but not for on-chip passive components. A low-pass filter which is composed of capacitors and resistors is one of the building blocks in PLL. In the past years, a low-pass filter is always designed off-chip to reduce the chip size and production cost. Nowadays, a low-pass filter integrated into a chip is preferred for SoC. However, these passive components will occupy large area in a chip. We usually use a smaller bandwidth in a spread spectrum clock generator (SSCG), thus it will lead to a larger low-pass filter in the SSCG system. Since we want to reduce these passive components, a novel divided-by-two circuit is proposed and used in the PLL.ABSTRACT ........................................................................................................i LIST OF FIGURES .......................................................................................................v LIST OF TABLES ....................................................................................................viii CHAPTER 1 INTRODUCTION........................................................................1 1.1 Motivation.....................................................................................................1 1.2 Thesis Organization.......................................................................................3 CHAPTER 2 BASIC OF PHASE LOCKED LOOP..........................................5 2.1 Building Blocks.............................................................................................5 2.1.1 Voltage Controlled Oscillator............................................................5 2.1.2 Phase Frequency Detector..................................................................6 2.1.3 Charge Pump......................................................................................9 2.1.4 Loop Filter.......................................................................................11 2.2 Phase Noise Performance Analysis.............................................................14 2.2.1 Noise at Input...................................................................................14 2.2.2 Noise of VCO..................................................................................15 2.3 Charge-Pump PLL Design..........................................................................17 2.3.1 Second-Order PLL...........................................................................17 2.3.2 Third-Order PLL..............................................................................20 2.3.3 Fourth-Order PLL............................................................................23 CHAPTER 3 BASIC OF SPREAD SPECTRUM CLOCK GENERATION...27 3.1 Spread Spectrum Clocking Fundamental Theory........................................27 3.2 Spread Spectrum Modes and Amounts........................................................29 3.3 Modulation Frequency.................................................................................30 3.4 Modulation Profile.......................................................................................30 3.5 Implementation of SSCG............................................................................31 iv 3.6 Timing Impacts of Spread Spectrum Clock.................................................32 3.6.1 Cycle-to-Cycle Jitter........................................................................33 3.6.2 Long-Term Jitter..............................................................................34 CHAPTER 4 DESIGN OF SPREAD SPECTRUM CLOCK GENERATOR..37 4.1 System Architecture.....................................................................................37 4.2 Voltage Controlled Oscillator......................................................................38 4.3 Phase/Frequency Detector...........................................................................41 4.4 Charge Pump...............................................................................................41 4.5 Programmable Charge Pump.......................................................................42 4.6 Loop Filter...................................................................................................43 4.7 Divided-by-Two Circuit..............................................................................45 4.8 Modular Programmable Prescaler...............................................................46 CHAPTER 5 SIMULATION RESULT OF SPREAD SPECTRUM CLOCK GENERATOR……………………......................................................................49 5.1 SSCG Behavior Simulation.........................................................................49 5.2 Circuit Level Simulation.............................................................................51 5.2.1 Simulation Results of Voltage Controlled Oscillator.......................51 5.2.2 Phase/Frequency Detector and Charge Pump..................................53 5.2.3 Frequency Divider...........................................................................55 5.2.4 Closed-Simulation of Spread Spectrum Clock Generator...............57 CHAPTER 6 CONCLUSION...........................................................................64 REFERENCE .....................................................................................................663721115 bytesapplication/pdfen-US展頻時脈鎖相迴路spread spectrum clockphase lock loopthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/57452/1/ntu-95-R93943117-1.pdf