黃鐘揚臺灣大學：電機工程學研究所黃俊輔Huang, Chun-FuChun-FuHuang2007-11-262018-07-062007-11-262018-07-062006http://ntur.lib.ntu.edu.tw//handle/246246/53487In this thesis, we proposed a quick register transfer level(RTL) front end for design analysis and verification. Our front end consists of three parts: (1) an RTL parser that supports most of the synthesizable Verilog subset and various library formats; (2) an elaborating process that generates control data flow graph(CDFG) and can be used for design intent extraction and (3) a logic synthesizer that translates the design into a word-level netlist and writes out a structural Verilog file. We have been able to read in several designs from other design teams and have verified the correctness of our front end by the Cadence Conformal Logic Equivalence Checker(LEC). With the word-level data structure and high-level design intent extraction at hand, we will be able to conduct more research on the design debugging and verification in the future.1 Introduction 8 1.1 Problem Description . . . . . . . . . . . . . . . . . 8 1.2 Previous Work . . . . . . . . . . . . . . . . . . . . 8 1.2.1 VIS . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2.2 Icarus Verilog. . . . . . . . . . . . . . . . . . . 9 1.3 Our Contribution. . . . . . . . . . . . . . . . . . . 10 1.3.1 A Powerful Front End. . . . . . . . . . . . . . . . 10 1.3.2 Design Analysis . . . . . . . . . . . . . . . . . . 10 1.3.3 Easy Extension. . . . . . . . . . . . . . . . . . . 10 2 The Basics of RTL Synthesis 11 2.1 Synthesis Flow Overview . . . . . . . . . . . . . . . 11 2.2 Data Structures. . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.1 HDL Parser. . . . . . . . . . . . . . . . . . . . . 11 2.2.2 Circuit . . . . . . . . . . . . . . . . . . . . . . 13 2.3 Modeling Issues . . . . . . . . . . . . . . . . . . . 14 3 Realization 19 3.1 Overview of The Framework . . . . . . . . . . . . . . 19 3.2 Control Flow Synthesis. . . . . . . . . . . . . . . . 20 3.2.1 Decription. . . . . . . . . . . . . . . . . . . . . 20 3.2.2 Statements without Condition. . . . . . . . . . . . 21 3.2.3 Statements under If Condition . . . . . . . . . . . 21 3.2.4 Statements under Case Condition . . . . . . . . . . 22 3.2.5 Statements under For Condition. . . . . . . . . . . 24 3.2.6 Mux v.s. Latch. . . . . . . . . . . . . . . . . . . 24 3.2.7 Carry-out Problemin Arithmetic Operations . . . . . 25 3.3 Always Statement. . . . . . . . . . . . . . . . . . . 26 3.3.1 Sequential Block. . . . . . . . . . . . . . . . . . 26 3.3.2 Combinational Block . . . . . . . . . . . . . . . . 27 3.3.3 Blocking and Non-blocking Assignments . . . . . . . 27 3.4 Continuous Assignments. . . . . . . . . . . . . . . . 27 3.5 Function. . . . . . . . . . . . . . . . . . . . . . . 28 3.5.1 Problem Description . . . . . . . . . . . . . . . . 28 3.5.2 Statement Ordering Problem in Function. . . . . . . 29 3.6 Bus Overlap Problem . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.6.1 Problem Description . . . . . . . . . . . . . . . . 30 3.6.2 Bus Overlap Situations . . . . . . . . . . . .. . . 30 3.6.3 Split Original Value . . . . . . . . . . . . . . .. 33 3.7 Parameter Overload Problem . . . . . . . . . . . . . .34 3.7.1 Problem Description . . . . . . . . . . . . . . . . 34 3.7.2 Module Instantiation with Parameter Overloading . . 35 3.7.3 Dynamic Overloading . . . . . . . . . . . . . . . . 35 3.7.4 Static Overloading . . . . . . . . . . . . . . . . 36 3.8 Tri-state Extraction . . . . . . . . . . . . . . . . . . . . . . . .37 4 Verication 38 4.1 Writing Structural Verilog Output . . . . . . . . . . 38 4.2 Experimental Setup . . . . . . . . . . . . . . . . . 43 4.3 Experimental Result . . . . . . . . .. . . . . . . . 47 4.3.1 AES . . . . . . . . . . . . . . . . . . . . . . . . 47 4.3.2 SDRAMController . . . . . . . . . . . . . . . . . . 50 4.3.3 Result Discussion . . . . . . . . . . . . . . . . . 53 5 Conclusion and Future Work 57 References 58 Appendices 60 A User’sManual 60 B Verilog BNF 611289399 bytesapplication/pdfen-US邏輯合成設計分析logic synthesisdesign analysisthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/53487/1/ntu-95-R93921109-1.pdf