郭大維臺灣大學:資訊工程學研究所呂維倫Lu, Wei-LunWei-LunLu2010-06-092018-07-052010-06-092018-07-052009U0001-0608200916215600http://ntur.lib.ntu.edu.tw//handle/246246/185411在行動裝置上雖然固態硬碟已經成為傳統硬碟的優秀替代品,但是由於效能和可靠度的關注而產生了嚴重的挑戰。此論文目標為針對具有低成本多層單元快閃記憶體之限制的提升效能之設計。一個有效率的快閃記憶體管理之設計被提出以管理具有快取支援的多個晶片之快閃記憶體,並且一個兩層的位址轉譯機制搭配一個有適應能力的快取決策被提出。本提出方法之效能由一個基於實際工作量和衡量標準之SystemC為基礎的固態硬碟模擬器所評估。評估結果顯示了本提出方法能夠顯著地提升不同硬體架構之多晶片固態硬碟的效能。Although solid-state disks seem being excellent alternatives to replace hard disks in mobile devices, serious challenges arise due to performance and reliability concerns. This work targets performance enhancement designs with the considerations of low-cost MLC flash memory. In particular, an efficient flash management design is proposed to manage multi-chipped flash memory with cache support, where a two-level address translation mechanism is presented with an adaptive caching policy. The capability of the proposed approach is evaluated with a SystemC-based solid-state-drive simulator based on realistic workloads and benchmarks. It was shown that the proposed approach could significantly improve the performance of multi-chipped solid-state disks over various hardware configurations.Abstract ixontents xiist of Figures xiiiist of Tables xv Introduction 1 System Architecture and Research Motivation 5.1 System Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Research Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 A Multi-Chipped FTL with Caching Support 9.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2 A Caching-Oriented Mapping Mechanism . . . . . . . . . . . . . . . . 11.2.1 Address Translation with Caching Support . . . . . . . . . . . 11.2.2 Heap-Like Index Structure . . . . . . . . . . . . . . . . . . . . 12.3 Access Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.1 An Adaptive Caching Policy . . . . . . . . . . . . . . . . . . . 14.3.2 Chain-Based Block Management . . . . . . . . . . . . . . . . . 16.3.3 Circular-Based Cleaner . . . . . . . . . . . . . . . . . . . . . . 19.4 Implementation Remarks . . . . . . . . . . . . . . . . . . . . . . . . . 21 Conclusion 23ibliography 25799930 bytesapplication/pdfen-US固態硬碟快閃記憶體轉譯層Solid-State DiskFTL多晶片固態硬碟之高效快閃記憶體轉譯層設計An Efficient FTL Design for Multi-Chipped Solid-State Disksthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/185411/1/ntu-98-R96922018-1.pdf