陳中平Chen, Chung-Ping臺灣大學:電子工程學研究所陳健峰Chen, Jian-FengJian-FengChen2010-07-142018-07-102010-07-142018-07-102008U0001-1707200822582000http://ntur.lib.ntu.edu.tw//handle/246246/189120靜態時序分析對奈米積體電路設計過程中是很重要的ㄧ環。在加快靜態時序分析速度的時候而準確度必須同時要兼顧。這篇論文主要針對靜態時序分析的兩個重要部份做探討，並對這些問題提出方法來解決。第一部份主要是要如何有效及精確的得到所有標準邏輯元件的行為模型。隨著標準邏輯元件越來越多，為了要維持準確度，大量的模擬資料需要被儲存起來，這勢必要耗費大量的記憶體空間，所以為了解決這些問題我們提出了壓縮資料方法。這方法壓縮率可以達19X並且空間節省95%，提高壓縮率的同時還維持該有的精確度。第二部份，先進製程中由於IC內部連線高阻抗導致其延遲主宰了整個電路的延遲。然而內部連線的寄生電容和電感所增加的效應影響信號的品質而且也提高了計算時的複雜度。針對這幾點我們提出快速遞迴卷積 (fast recursive convolution) 方法模擬。經過實驗發現最後的結果準確度很高，最後結果跟SPICE比較誤差小於1%，速度也比SPICE快一千倍。Static Timing Analysis (STA) is very important for nanometer integrated circuit design. The accuracy of STA still needs to be improved while minimizing runtime penalty. This thesis focuses on two important aspects of STA. First, an efficient and accurate method is needed for obtaining the behavior model of all standard cells. With the existing large number of standard cells, a substantial amount of simulation data has to be recorded to maintain the accuracy. This in turn results in an unbearable amount of memory overhead. We present a method to compress the large gate timing information, to minimize the amount of memory overhead. A compression ratio of 19X and a Space Saving of 95% can be achieved and the compacted data still maintained a very high level of accuracy. Second, the interconnect delay dominates the circuit path delay for today''s CMOS technology due to the effect of the high impedance interconnect. However, parasitic capacitance and inductance in interconnections have begun to increasingly affect the signal quality and the computed complexity. We present a new fast recursive convolution method for timing simulation. Experimental results show very accurate result of 1% error and one thousand times faster runtime when compared with SPICE.Chapter 1 Introduction 1 1.1 Gate Timing Model Characterization and Compression 1 1.2 Interconnect Simulation Algorithm 2hapter 2 Gate Timing Model Characterization 4 2.1 Geometric Spacing 5 2.2 Input Characterization Waveform 6 2.3 Operating Range of Cells 7 2.4 Output Voltage Waveform 8hapter 3 Gate Timing Model Compression 9 3.1 Compression with the Singular Value Decomposition Method 9 3.1.1 Introduction to the SVD Theory 10 3.1.2 Current Library Compaction with SVD 10 3.2 Further Compression with Fast Fourier Transform 16 3.2.1 Data Structure of the Fourier Coefficients 21 3.3 Experimental Results 22 3.3.1 A Comparison of Compacted Data and Original Data 22 3.3.2 Signal Quality and Compression Ratio 28 3.4 Waveform Interpolation 30 3.5 Model Characterization and Compression Flow 31hapter 4 Interconnect Simulation Algorithm 33 4.1 Generation of Moments for R-L-C Interconnect 33 4.2 Moment Matching Method 35 4.3 Recursive Convolution Method 40 4.3.1 Related Work 40 4.3.2 High-Order Equation-based Recursive Convolution 42 4.4 Ordinary Differential Equation-based Recursive Convolution 44 4.5 Experimental Results 45hapter 5 Future Work 54 5.1 Gate Timing Model Characterization and Compression 54 5.2 Interconnect Simulation Algorithm 55hapter 6 Conclusion 56ibliography 57763982 bytesapplication/pdfen-US電流源模型資料壓縮閘延遲內部連線延遲時序分析遞迴卷積電路模擬Current Source ModelData compressionGate delayInterconnect delayTiming analysisRecursive convolutionCircuit simulationthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/189120/1/ntu-97-R95943167-1.pdf