A novel 0.7 V two-port 6T SRAM memory cell structure with single-bit-line simultaneous read-and-write access (SBLSRWA) capability using partially-depleted SOI CMOS dynamic-threshold technique

Dept. of Electr. Eng., National Taiwan Univ.Liu, S.C.S.C.LiuKuo, J.B.J.B.Kuo2007-04-192018-07-062007-04-192018-07-061999-10http://ntur.lib.ntu.edu.tw//handle/246246/2007041910021584application/pdf115951 bytesapplication/pdfen-USA novel 0.7 V two-port 6T SRAM memory cell structure with single-bit-line simultaneous read-and-write access (SBLSRWA) capability using partially-depleted SOI CMOS dynamic-threshold techniquejournal article10.1109/SOI.1999.819860http://ntur.lib.ntu.edu.tw/bitstream/246246/2007041910021584/1/00819860.pdf