Dept. of Electr. Eng., National Taiwan Univ.Chang, Hao-ChiehHao-ChiehChangChen, Li-LinLi-LinChenLian, Chung-JrChung-JrLianChang, Yung-ChiYung-ChiChangLIANG-GEE CHEN2007-04-192018-07-062007-04-192018-07-061999-08http://ntur.lib.ntu.edu.tw//handle/246246/2007041910021566https://www.scopus.com/inward/record.uri?eid=2-s2.0-47349104554&doi=10.1109%2fAPASIC.1999.824048&partnerID=40&md5=747907ef9dc65af756419c928ed97966IP design of a complete, reconfigurable baseline JPEG encoder is presented in this paper. It features completely JFIF (JPEG File Interchange Format) compatible bit-stream output and a user-defined quantization table that can be re-configured at the run time and the compiling time. Thus, various hardware configurations can be easily achieved. Besides, modularized design is practiced such that smooth data flow in this pipelined architecture can be easily achieved by utilizing a central controller. This technique improves system performance greatly. © 1999 IEEE.application/pdf349959 bytesapplication/pdfen-USconference paper10.1109/APASIC.1999.8240482-s2.0-47349104554http://ntur.lib.ntu.edu.tw/bitstream/246246/2007041910021566/1/00824048.pdf