劉深淵臺灣大學：電子工程學研究所朱虹霖Chu, Hong-LinHong-LinChu2007-11-272018-07-102007-11-272018-07-102007http://ntur.lib.ntu.edu.tw//handle/246246/57561這篇論文的內容在於，應用於被動光纖網路之突發式接收器的動機、挑戰、和方法。 先介紹為何需要接收器。再來則是對於被動光纖網路的解說，從而了解為何需要突發式接收器。第一章的重點在於動機，除了動機之外，也有被動光纖網路的規格簡介。 將現有文獻的突發式資料時脈回復電路分為三大類後，分別解說其運作方式。在了解這些基本架構之後，以可達到的傳輸率、鎖定時間、功率、面積、和時間抖動的特性去比較這三大類的優缺點。 在本論文中，第一個作品為一利用過度偵測(excessive-bottom-hold)的突發式轉阻放大器，在高速(10Gb/s)下，可有非常快的穩定時間(10bits)，很大的動態輸入範圍(42.5dB)，以及低功率損耗(7.2mW)。這一次實作是以0.13微米的標準互補式金氧半製程實現，總面積為1.2756 x 0.625mm2。 第二個作品則是利用閘式壓控振盪器(Gated Voltage-Controlled Oscillator)及資料上升緣取出器(data-rising-edge extractor)來形成的突發式時脈資料回復電路，四分之一速率的架構可使此突發式時脈資料回復電路操作在高速(10Gb/s)時，不必使用電感並且同時有低功率消耗。此實作是以0.13微米的標準互補式金氧半製程實現，總面積為1.461 x 1.291mm2。In this thesis, the motivation, challenges, and solutions of burst-mode receiver (BMRX) for passive optical networks (PONs) are presented. The need for optical receiver is explained first. Then, the basic architecture of a PON is introduced so that the need for BMRX can be understood. The motivation and the specifications related to burst-mode clock and data recovery (BMCDR) circuits are also introduced. The existing BMCDR circuits are classified into three categories in this thesis. After introducing every category, a comparison in view of achievable data rate, locking time, power, area, and jitter performance is made. Summarizing the comparisons, the challenges manifest clearly. The first work is a burst-mode transimpedance amplifier (BMTIA), utilizing excessive-bottom-hold circuit. This 10Gb/s BMTIA behaves quick settling time (10bits), wide dynamic range (42.5dB), and low power consumption (7.2mW). This circuit is implemented in a standard 0.13um CMOS process and the area is 1.2756 x 0.625 mm2. The second work is a quarter-rate burst-mode clock and data recovery (BMCDR) circuit, utilizing gated voltage-controlled oscillator (GVCO) and data-rising-edge extractor. The quarter-rate operation makes this BMCDR to work at 10Gb/s with low power consumption and no inductor is used. This circuit is implemented in a standard 0.13um CMOS process and the area is 1.461 x 1.291mm2.1. Introduction 1 1.1 Passive Optical Network 1 1.2 Specifications 6 1.2.1 General PON specifications 7 1.2.2 Jitter performance 7 1.2.3 Mask of eye diagram for upstream transmission 8 1.3 Thesis Organization 9 2. Categories of Burst-Mode Clock and Data Recovery Circuits 11 2.1 Phase-Locked-Loop-Based Burst-Mode Clock and Data Recovery Circuit 13 2.2 Phase-Picking Burst-Mode Clock and Data Recovery Circuit 18 2.3 Gated Voltage-Controlled Oscillator-Based Burst-Mode Clock and Data Recovery Circuit 22 2.4 Comparison 24 2.4.1 Data rate and locking time 24 2.4.2 Power and area 27 2.4.3 Jitter characteristics 27 2.4.3.1 Jitter transfer 28 2.4.3.2 Jitter tolerance 30 2.4.3.3 Jitter generation 32 2.5 Summary 33 3. A 10Gb/s Burst-Mode Transimpedance Amplifier 35 3.1 System Architecture 36 3.2 Core TIA Architecture 37 3.2.1 Small-signal analysis for TIA 38 3.3 Excessive-Bottom-Hold Circuit 40 3.4 Simulation Results 43 3.5 Experimental Results 47 3.6 Conclusions 51 4. A 10Gb/s Inductorless Quarter-Rate Burst-Mode Clock and Data Recovery 53 4.1 System Architecture 55 4.2 Circuit Description 56 4.2.1 Data-Rising-Edge Extractor 56 4.2.2 90º-lag GVCO 58 4.3 Methodology For Xº-lag GVCO 63 4.4 Simulation Results 72 4.5 Experimental Result 75 4.6 Conclusions 79 5. Conclusions 82 Bibliography 832716661 bytesapplication/pdfen-US被動光纖網路突發式接收器Passive optical networksBurst-modeReceiverthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/57561/1/ntu-96-R94943091-1.pdf