Yang YTzou MTAI-CHENG LEE2023-06-092023-06-09202215497747https://www.scopus.com/inward/record.uri?eid=2-s2.0-85128656601&doi=10.1109%2fTCSII.2022.3169006&partnerID=40&md5=f99442ace0567a75e41bc3502738c302https://scholars.lib.ntu.edu.tw/handle/123456789/632323A reference-less sub-baud-rate linear clock and data recovery with a frequency acquisition is proposed to operate from 6 to 11 Gb/s. The proposed frequency acquisition technique operating at a single differential quarter-rate clock and sharing the same phase detector achieves low power consumption. Fabricated in a 28-nm CMOS technology, the frequency detection (FD) logic and locked detector (LD) consume only 0.62 mW. Furthermore, the proposed sub-baud-rate linear phase detector with dead zone free guarantees the in-band recovered phase noise and needs no accuracy reference voltage threshold for phase locking. The proposed sub-baud-rate CDR consumes 8.66 mW, corresponding to power efficiency of 0.86 pJ/bit at 10 Gb/s. IEEECircuits and systems; Clock and data recovery (CDR); Clocks; Detectors; frequency acquisition technique; Jitter; Power demand; reference-less CDR; sample-and-hold PD.; Sub-baud-rate CDR; Threshold voltage; Voltage-controlled oscillatorsCircuit oscillations; Clocks; Electric power utilization; Jitter; Locks (fasteners); Oscillistors; Phase comparators; Phase noise; Recovery; Signal detection; Threshold voltage; Timing circuits; Variable frequency oscillators; Baud rate; Circuits and systems; Clock and data recovery; Frequency acquisition; Frequency acquisition technique; Power demands; Reference-less clock and data recovery; Sample and hold; Sample-and-hold PD.; Sub-baud-rate clock and data recovery; Clock and data recovery circuits (CDR circuits)journal article10.1109/TCSII.2022.31690062-s2.0-85128656601