李致毅臺灣大學：電子工程學研究所吳昇翰Wu, Sheng-HannSheng-HannWu2007-11-272018-07-102007-11-272018-07-102006http://ntur.lib.ntu.edu.tw//handle/246246/57572在這裡提出以0.18-um CMOS製程所製作20-GHz時脈倍頻單元, 應用於OC-768系統上, 採用雙迴路及三階濾波器以消除Jitter的影響. 所設計之電路達到輸出Jitter 0.2ps,rms及 4.5ps,pp同時在1.8V的偏壓下消耗40mW.A 20-GHz clock multiplication unit for SONET OC-768 systems employs dual loops and third-order loop filter to suppress the jitter. Realized in 0.18-um CMOS technology, this circuit achieves an output jitter of 0.2 ps,rms and 4.5 ps,pp while consuming 40 mW from a 1.8-V supply.CHAPTER 1 Introduction 1.1 Next Generation .............................................................................................. p.01 1.2 Thesis Organization ........................................................................................ p.02 CHAPTER 2 General Consideration 2.1 Clock multiplication unit .................................................................................. p.05 2.1.1 Phase and Frequency Detector ................................................................. p.06 2.1.2 Charge pump and Loop Filter .................................................................. p.07 2.1.3 Voltage Controlled oscillator ................................................................... p.10 2.1.4 Frequency Divider ................................................................................... p.11 2.2 General Analysis Techniques for PLL ............................................................. p.13 2.1.1 Dynamics Mathematical Model .............................................................. p.13 2.1.2 Phase Noise ............................................................................................. p.15 CHAPTER 3 A 20-GHz Clock Multiplication Unit 3.1 Architecture and Building Blocks ................................................................... p.19 3.1.1 PD and V/I Converter ............................................................................. p.21 3.1.2 Frequency Detector ................................................................................. p.22 3.1.3 VCO/Divider/Buffer ............................................................................... p.23 3.2 Consideration ................................................................................................... p.24 3.2.1 Reference Feedthrough ........................................................................... p.24 3.2.2 Acquisition Range ................................................................................... p.11 3.4 Simulation Results ........................................................................................... p.33 3.3.1 Phase detector with V/I converter ........................................................... p.33 3.3.2 Voltage controlled oscillator .................................................................... p.33 3.3.3 Frequency divider .................................................................................... p.35 3.3.4 System analysis ........................................................................................ p.36 3.4 Experiment Results ........................................................................................... p.41 CHAPTER 4 Conclusions ................................................................................................ p.47 Bibliography ............................................................................................. p.493344675 bytesapplication/pdfen-US鎖相迴路時脈倍頻單元CMUPLLOC-768thesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/57572/1/ntu-95-R93943080-1.pdf