林茂昭臺灣大學：電信工程學研究所呂明哲Lu, Ming-CheMing-CheLu2007-11-272018-07-052007-11-272018-07-052005http://ntur.lib.ntu.edu.tw//handle/246246/58790根據以往之研究，我們知道迴旋碼 (Convolutional code) 跟隨延遲處理器 (A delay processor) 及信號點對應器 (A Signal mapper) 的組合能建構出具有大自由距離的迴旋碼。所以很自然的把延遲處理器及信號點對應器的組合應用到低密度同位檢查 (Low-density parity check, LDPC) 碼上試圖達到更大的自由距離。 根據我們提出的架構，我們設計一個兩層的延遲處理器及兩種不同的解碼方法，分別是介紹在４．２節的原始解碼器 (Original decoder) 及５．１節的遞迴解碼器 (Iterative decoder)。模擬結果顯示使用原始解碼器去解兩層的延遲處理器，其結果從中到高訊雜比效能皆不錯，但是在訊雜比低時，會有錯誤蔓延 (Error Propagation) 的問題產生而導致效能很差。因此我們提出遞迴解碼器去解決此問題，而模擬的結果顯示使用遞迴解碼器不但能改善錯誤率從中到高訊雜比，而且於低訊雜比的部分也能有改善As indicated in [12], we observe that a delay processor and a signal mapper following the encoder of a convolutional code C can result in a convolutional code C of large free distances. It is natural to consider once again applying a delay processor and a signal mapper to the output of the low-density parity check (LDPC) code to achieve large free distance. With the proposed scheme, we show a design for a 2-level delay processor. And we proposed two decoding methods, ”original decoder” and ”iterative decoder”, in sec. 4.2 and sec. 5.1, respectively. Simulation results show that the performance of a 2-level delay processor with original decoder is good at moderate to high SNRs, but poor at low SNR owing to the problem of the error propagation. To overcome this problem, iterative decoder was proposed. Simulation results show that the performance of a 2-level delay processor with iterative decoder is good not only at moderate to high SNR, but also at low SNR.1 Introduction 1 2 Reviews on LDPC Codes 3 2.1 Representation of LDPC codes . . .. . . . . . . . . . 3 2.2 EncodingMethods . . . . . . . . . . . . . . . . . . . 6 2.3 DecodingMethods . . . . . . . . . . . . . . . . . . . 7 2.3.1 Gallager’s hard-decision decoding [1] . . . . . . 7 2.3.2 Sumproduct algorithm(SPA) . . . . . . . . . . . . . 8 3 Some LDPC Code Constructions 11 3.1 Regular LDPC Codes . . . . . . . . . . . . . . . . 11 3.1.1 Gallager’s Codes . . . . . . . . . . . . . . . . 11 3.1.2 Mackay’s Codes . . . . . .. . . . . . . . . . . . 12 3.1.3 Finite Geometries LDPC Codes . . . . . . . . . . . 13 3.2 Irregular LDPC Codes . . . . . . . . . . . . . . . . 20 3.3 Construction of Irregular LDPC Codes Based on Masked EG-Gallager LDPC codes[11] . . . . . . . . . . . . . . . 21 4 LDPC Codes with Inter-block Memories 32 4.1 A Delay Processor Scheme . . . . . . . . . . . . . . 33 4.2 Combine LDPC Codes with a Delay Processor Scheme . . 35 4.3 Simulations . . . . . . . . . . . . . . . . . . . . . . .38 4.4 A Modified Encoding and Decoding System . . . . . . . 45 5 Iterative Decoding for LDPC Codes with a Delay Processor Scheme 47 5.1 The Proposed Iterative Coding Scheme . . . . . . . . 47 5.2 Simulations . . . . . . . . . . . . . . . . . . . . . . 52 6 Conclusions 57 A Some Detail of the simulation 58806908 bytesapplication/pdfen-US低密度同位檢查碼延遲處理器遞迴解碼器LDPCDelay processorIterative decoderthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/58790/1/ntu-94-R92942037-1.pdf