PEI YUN TSAIChen, Wei-TzuoWei-TzuoChenLin, Xing-ChengXing-ChengLinHuang, Meng-YuanMeng-YuanHuang2024-09-182024-09-182010https://www.scopus.com/record/display.uri?eid=2-s2.0-77955997174&origin=resultslisthttps://scholars.lib.ntu.edu.tw/handle/123456789/721443Paris, 30 May 2010 through 2 June 2010In this paper, a VLSI architecture of a reduced-complexity K-best sphere decoder is designed, which aims to solve the 4 x 4 64-QAM multiple-input multiple-output (MIMO) signal detection problems in high-speed applications. We propose a fully-pipelined sorter, which can generate one result per clock cycle and thus greatly enhance the detection throughput. On the other hand, various K values are adopted at each layer to save the hardware complexity. The proposed design has been implemented in 0.18 μm CMOS technology and has 366K gates. From post-layout simulation, this work achieves a detection rate of 1.5 Gbps at 62.5-MHz clock frequency. ©2010 IEEE.[SDGs]SDG7conference paper10.1109/ISCAS.2010.55376752-s2.0-77955997174