Low jitter and multi-rate clock and data recovery circuit using a MSADLL for chip-to-chip interconnection

Hsiang-Hui ChangRong-Jyi YangSHEN-IUAN LIU2018-09-102018-09-102004-12http://scholars.lib.ntu.edu.tw/handle/123456789/310600[SDGs]SDG7Low jitter and multi-rate clock and data recovery circuit using a MSADLL for chip-to-chip interconnectionjournal article10.1109/tcsi.2004.8381472-s2.0-10944263801WOS:000225484600003